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ARCHITECTURE
Instruction cycle
WHAT IS AN INSTRUCTION CYCLE?
Also called fetch, decode and execute cycle.
It is the process by which a computer retrieves a
program instruction from its memory,
determines what actions
the instruction dictates, and carries out those
actions.
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KEY TERMS
PC
Program Counter
Keep track of instruction to be executed next.
MAR
Memory Address Register
Holds address of memory block to be read or written
to.
MDR / MBR
Memory Data Register / Memory Buffer Register
A two data registers that holds data fetched from
memory or data to be stored in memory
CIR
Current Instruction Register
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A temporary holding ground for instruction just
fetched from memory
Fetch
Memor
PC
CPU y
incremented by Copy of
1 Copy of address of instruction in
PC next instruction
MAR memory
address held in
MAR
MDR
Instruction
CI
R4
Decode
CPU
PC MAR
MDR
CI
R5
Split instruction into operation code & address
if present. Then decode operation code.
Execute
CPU
PC MAR
MDR
Execute
instruction
CI
R6
1. Load the address of next instruction in the PC
into the MAR.
So that the control unit can fetch the instruction from
the right part of the memory.
2. Copy the instruction/data that is in the memory
address given by the MAR into the MDR.
MDR is used whenever anything is to go from the CPU
Fetch to main memory, or vice versa.
3. Increment the PC by 1.
So that it contains the address of the next instruction,
assuming that the instructions are in consecutive
locations.
4. Load the instruction/data that is now in the MDR
into the CIR.
Thus the next instruction is copied from memory ->
MDR -> CIR.
Decode 5. Contents of CIR split into operation code and
address if present e.g. store, add or jump
instructions.
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6. Decode the instruction that is in the CIR.
If the instruction is an output (from memory)
instruction then:
Execute Copy address part of part of the instruction (of data to
output) in CIR into MAR.
Output contents of MDR.