Intro to Boundary-Scan

(JTAG)
 Outline
• What is 1149.1?
• 1149.1 Basics
• Documentation & Resources
• 1149.1 for the Designer
• Extended Uses for the TAP Controller
IEEE 1149.1 Boundary-Scan
• Facilitates board testing
• Provides an on-chip means of
controlling and testing pads
• Boundary-scan components can also be
used for other test purposes:
– Logic and RAM BIST control
– Scan chain control
– Scan wrapper config., test modes, etc.
Intro To Boundary-Scan 4
Intro To Boundary-Scan 5
 Pad & Parametric Test
• 1149.1 can be used to control and
exercise pads independent of the chip
core
• Leakage on tri-state outputs
• Measure voltage and current for output
pads driving 0 or 1
• Test logic levels captured by input pads
at various voltages
 Outline
• What is 1149.1?
• 1149.1 Basics
• Documentation & Resources
• 1149.1 for the Designer
• Extended Uses for the TAP Controller
 1149.1 Hardware
• Test Access Port: 5 pins
• TAP Controller
– Finite State Machine
– Internal registers (Bypass, Instruction, etc.)
– Test control logic
• Boundary-Scan Register Chain
• Internal Data Registers (Optional)
 Boundary-Scan Components
I

TMS
O
TDI
TAP Chip
TCK Controller Core
TDO

TRST_N

9
 TAP Controller Components
SI SO

Bypass Reg.
TDI
Instruction Register

TMS Various TAP

Outputs:
Finite Instruction UpdateDR,
TCK State Decode CaptureDR,
Machine TriState,
TRST_N Etc.

TDO

10
Intro To Boundary-Scan 11
1
TAP Controller State Diagram
Test-Logic-Reset
0
1 1
Run-Test/Idle Select-DR-Scan Select-IR-Scan
0 0 0
1 Capture-DR 1 Capture-IR
0 0
0 0
Shift-DR Shift-IR
1 1
Exit1-DR 1 Exit1-IR 1
0 0
0 0
Pause-DR Pause-IR
1 1
0 Exit2-DR 0 Exit2-IR
1 1
Update-DR Update-IR
1 0 1 0
Intro To Boundary-Scan 13
Intro To Boundary-Scan 14
 BYPASS Instruction
• A mandatory instruction
• The default instruction for TAPs with no
IDCODE register
• Short scan path: 1 bit between TDI and
TDO
• Usually loaded in chips that are idle
while other chips on the board are being
tested
15
 BYPASS Data Path
SI SO

Bypass Reg.
TDI
Instruction Register

TMS
Finite Instruction
TCK State Decode
Machine

TRST_N

TDO

16
EXTEST & SAMPLE/PRELOAD
• EXTEST is the “workhorse” JTAG instruction
– Sample (“Capture”) & Drive (“Update”) output
signals
– Sample & optionally drive input signals
• Data is first loaded into boundary register
chain with SAMPLE/PRELOAD instruction
– Samples inputs and outputs, pass-through
– Loads boundary register with data

17
 SAMPLE/PRELOAD: Start

SAMPLE/
PRELOAD

TMS

TDI TAP
Controller Chip
TCK
Core
BYPASS
TDO

TRST_N

18
1
TAP Controller State Diagram
Test-Logic-Reset
0
1 1
Run-Test/Idle Select-DR-Scan Select-IR-Scan
0 0 0
1 Capture-DR 1 Capture-IR
0 0
0 0
Shift-DR Shift-IR
1 1
Exit1-DR Exit1-IR
0 0
0 0
Pause-DR Pause-IR
1 1
0 Exit2-DR 0 Exit2-IR
1 1
Update-DR Update-IR
1 0 1 0
 Instruction Register Data Path
SI SO

Bypass Reg.
TDI
Instruction Register
TMS

Finite Instruction
TCK State Decode
Machine
TRST_N

TDO

20
1
TAP Controller State Diagram
Test-Logic-Reset
0
1 1 Select-IR-Scan
Run-Test/Idle Select-DR-Scan
0 0 0
1 Capture-DR 1 Capture-IR
0 0
0 0
Shift-DR Shift-IR
1 1
Exit1-DR Exit1-IR
0 0
0 0
Pause-DR Pause-IR
1 1
0 Exit2-DR 0 Exit2-IR
1 1
Update-DR Update-IR
1 0 1 0
 SAMPLE/PRELOAD:
UpdateIR
SAMPLE/
DATA
PRELOAD

TMS
TDI TAP
Controller Chip
TC Core
K BYPASS
SMP/PRLD
TDO
TRST_N

22
1
TAP Controller State Diagram
Test-Logic-Reset
0
1 1
Run-Test/Idle Select-DR-Scan Select-IR-Scan
0 0 0
1 Capture-DR 1 Capture-IR
0 0
0 0
Shift-DR Shift-IR
1 1
Exit1-DR Exit1-IR
0 0
0 0
Pause-DR Pause-IR
1 1
0 Exit2-DR 0 Exit2-IR
1 1
Update-DR Update-IR
1 0 1 0
 SAMPLE/PRELOAD: CaptureDR
Capture (sample)

0 1 0 1
DATA
Mode=0

TMS 0
TDI TAP
Controller Chip 1
TC Core
K SMP/PRLD
TDO 0
TRST_N
0 1 0 1

24
1
TAP Controller State Diagram
Test-Logic-Reset
0
1 1
Run-Test/Idle Select-DR-Scan Select-IR-Scan
0 0 0
1 Capture-DR 1 Capture-IR
0 0
0 0
Shift-DR Shift-IR
1 1
Exit1-DR Exit1-IR
0 0
0 0
Pause-DR Pause-IR
1 1
0 Exit2-DR 0 Exit2-IR
1 1
Update-DR Update-IR
1 0 1 0
 SAMPLE/PRELOAD: ShiftDR

01 0
1 1
0 1
0
DATA

TMS
0
1
TDI TAP
Controller Chip 10
TCK
Core
SMP/PRLD
TDO
1
0
TRST_N

1 1
0 0
1 0
1 1
0
0
1
0

26
1
TAP Controller State Diagram
Test-Logic-Reset
0
1 1
Run-Test/Idle Select-DR-Scan Select-IR-Scan
0 0 0
1 Capture-DR 1 Capture-IR
0 0
0 0
Shift-DR Shift-IR
1 1
Exit1-DR Exit1-IR
0 0
0 0
Pause-DR Pause-IR
1 1
0 Exit2-DR 0 Exit2-IR
1 1
Update-DR Update-IR
1 0 1 0
 SAMPLE/PRELOAD:
UpdateDR
1 0 1 0
Mode=0

TMS
1
TDI TAP
Controller Chip 0
TCK
Core
SMP/PRLD
TDO
1
TRST_N
1 0 1 0

28
1
TAP Controller State Diagram
Test-Logic-Reset
0
1 1
Run-Test/Idle Select-DR-Scan Select-IR-Scan
0 0 0
1 Capture-DR 1 Capture-IR
0 0
0 0
Shift-DR Shift-IR
1 1
Exit1-DR Exit1-IR
0 0
0 0
Pause-DR Pause-IR
1 1
0 Exit2-DR 0 Exit2-IR
1 1
Update-DR Update-IR
1 0 1 0
 EXTEST: UpdateIR

1 0 1 0
EXTEST
Mode=1

TMS
1
TDI TAP
Controller Chip 0
TCK
Core
EXTEST
TDO
1
TRST_N
1 0 1 0

30
1
TAP Controller State Diagram
Test-Logic-Reset
0
1 1
Run-Test/Idle Select-DR-Scan Select-IR-Scan
0 0 0
1 Capture-DR 1 Capture-IR
0 0
0 0
Shift-DR Shift-IR
1 1
Exit1-DR Exit1-IR
0 0
0 0
Pause-DR Pause-IR
1 1
0 Exit2-DR 0 Exit2-IR
1 1
Update-DR Update-IR
1 0 1 0
 EXTEST: CaptureDR
Capture (sample)

1 0
1 1 0
1
DATA

TMS
1
TDI TAP
Controller Chip 0
1
TCK
Core
EXTEST
TDO
1
TRST_N
1 0
1 1 1
0

32
1
TAP Controller State Diagram
Test-Logic-Reset
0
1 1
Run-Test/Idle Select-DR-Scan Select-IR-Scan
0 0 0
1 Capture-DR 1 Capture-IR
0 0
0 0
Shift-DR Shift-IR
1 1
Exit1-DR Exit1-IR
0 0
0 0
Pause-DR Pause-IR
1 1
0 Exit2-DR 0 Exit2-IR
1 1
Update-DR Update-IR
1 0 1 0
 EXTEST: ShiftDR

0
1 0
1 0
1 0
1
DATA

TMS
0
1
TDI TAP
Controller Chip 0
1
TCK
Core
EXTEST
TDO
0
1
TRST_N

1 0
1 0
1 0
1 0
1
1
1
1

34
1
TAP Controller State Diagram
Test-Logic-Reset
0
1 1
Run-Test/Idle Select-DR-Scan Select-IR-Scan
0 0 0
1 Capture-DR 1 Capture-IR
0 0
0 0
Shift-DR Shift-IR
1 1
Exit1-DR Exit1-IR
0 0
0 0
Pause-DR Pause-IR
1 1
0 Exit2-DR 0 Exit2-IR
1 1
Update-DR Update-IR
1 0 1 0
 EXTEST: UpdateDR

0 0 0 0
DATA
Mode=1

TMS
0
TDI TAP
Controller Chip 0
TCK
Core
EXTEST
TDO
0
TRST_N
0 0 0 0

36
Intro To Boundary-Scan 37
Intro To Boundary-Scan 38
Intro To Boundary-Scan 39
Intro To Boundary-Scan 40
Intro To Boundary-Scan 41
Intro To Boundary-Scan 42
Intro To Boundary-Scan 43
 Outline
• What is 1149.1?
• 1149.1 Basics
• Documentation & Resources
• 1149.1 for the Designer
• Extended Uses for the TAP Controller

44
Boundary-Scan Documentation
• IEEE Standard:
– IEEE Std 1149.1-1990 & 1149.1a-1993:
“IEEE Standard Test Access Port and
Boundary-Scan Architecture”
– IEEE Std 1149.1b-1994:
“Supplement to IEEE Std 1149.1-1990 ….”
(BDSL)
– IEEE Std 1149.1-2001
• “The Boundary-Scan Handbook”,
Second Edition (1998), by Ken Parker
45
 Outline
• What is 1149.1?
• 1149.1 Basics
• Documentation & Resources
• 1149.1 for the Designer
• Extended Uses for the TAP Controller

46
 Beyond Board-Test:
Extending the TAP Controller
• The TAP Controller runs the show for
boundary-scan and other TAP-based tests
• Some TAP-based test functions have
become increasingly complex & specialized
– Test signal control
– BIST control and capture
– Scan shifting
• Most functions are based on TAP registers
47
 Static Register: IDCODE
• 32 Bits predefined in 1X
0X
internal register: 1X
0X
– Version (4 bits)
V P M 1
– Part Number (16 bits) TDI

– Manufacturer (11 bits) 0

– LSB is set to 1 TDO

• Scan out through 1

0V
TDO during IDCODE 1P Instruction: BYPASS
IDCODE
0M
instruction 01

48
 Update-Only: User Register
TAP State: UpdateDR
• General-purpose bits 1
0
10
00
• User defines and 1
1
10
10
connects signals 0 0 1
1 0 1
0
• Scan in a value TDI

(through TDI) to set

• Used for test modes, TDO

configurable logic, 0
0 Instruction: SELUSER
etc. 0
0
• No capture capability
49
 Capture/Update Register:
RAMBIST
• Capture and update 1
1
capability 1
0
• User-defined signals: R0

– Drive RAMBIST enable TDI 11 01 11 X

1
0
R1
– Read RAMBIST results
R2
• Scan in a value TDO
X
1 R3
(through TDI) to set 0
4
Instruction: TAP State:
• Scan out results 1
X SELRAMBIST
RUNRAMBIST ScanDR
UpdateDR
RunTest
CaptureDR
ScanDR
through TDO
50