Semiconductor Manufacturing Technology: Oxidation

Semiconductor
Manufacturing Technology
Michael Quirk & Julian Serda
© October 2001 by Prentice Hall
Chapter 10
Oxidation
Semiconductor Manufacturing Technology © 2000

2001 by Prentice Hall
by Michael Quirk and Julian Serda
Objectives
After studying the material in this chapter, you will be able to:
1. Describe an oxide film for semiconductor manufacturing,

including its atomic structure, how it is used and its benefits.
2. State the chemical reaction for oxidation and describe how
oxide grows on silicon.
3. Explain selective oxidation and give two examples.
4. State the three types of thermal processing equipment, describe
the five parts of a vertical furnace, and give the attributes of a
fast ramp vertical furnace.
5. Explain what is a rapid thermal processor, its usage and design.
6. Describe the critical aspects of the oxidation process, its quality
measures and some common troubleshooting problems.
Semiconductor Manufacturing Technology © 2001 by Prentice Hall
Diffusion Area of Wafer Fabrication
Wafer fabrication (front-end)
Wafer start
Thin Films Polish
Unpatterned
wafer
Completed wafer Diffusion Photo Etch
Test/Sort Implant
Used with permission from Advanced Micro Devices
Semiconductor Manufacturing Technology Figure 10.1 © 2001 by Prentice Hall

Oxide Film
• Nature of Oxide Film

• Uses of Oxide Film
– Device Protection and Isolation
– Surface Passivation
– Gate Oxide Dielectric
– Dopant Barrier
– Dielectric Between Metal Layers

Atomic Structure of Silicon Dioxide
Silicon Oxygen
Used with permission from International SEMATECH

Field Oxide Layer
Field oxide isolates active regions from each other.
n-well p-well
p- Epitaxial layer
p+ Silicon substrate

Gate Oxide Dielectric
Polysilicon gate
Gate Oxide
n-well p-well
p- Epitaxial layer

Oxide Layer Dopant Barrier
Phosphorus implant
Barrier oxide
n-well
p- Epitaxial layer

Table 10.1
Oxide Applications: Native Oxide
Purpose: This oxide is a contaminant and generally

undesirable. Sometimes used in memory storage or
film passivation.
Silicon dioxide (oxide)
Comments: Growth rate at room temperature is 15 per hour up

to about 40 Å.
Semiconductor Manufacturing Technology Table 10.1A © 2001 by Prentice Hall

Table 10.1
Oxide Applications: Field Oxide
Purpose: Serves as an isolation barrier between individual

transistors to isolate them from each other.
Field oxide
Transistor site
Comments: Common field oxide thickness range from 2,500 Å

to 15,000 Å. Wet oxidation is the preferred method.
Semiconductor Manufacturing Technology Table 10.1B © 2001 by Prentice Hall

Table 10.1
Oxide Applications: Gate Oxide
Purpose: Serves as a dielectric between the gate and source-

drain parts of MOS transistor.
Gate oxide Gate
Source Drain
Transistor site
Comments: Growth rate at room temperature is 15 Å per hour

up to about 40 Å. Common gate oxide film
thickness range from about 30 Å to 500 Å. Dry
oxidation is the preferred method.
Semiconductor Manufacturing Technology Table 10.1C © 2001 by Prentice Hall
Table 10.1
Oxide Applications: Barrier Oxide
Purpose: Protect active devices and silicon from follow-on

processing.
Barrier oxide
Metal
Diffused resistors
Comments: Thermally grown to several hundred Angstroms

thickness.
Semiconductor Manufacturing Technology Table 10.1D © 2001 by Prentice Hall
Table 10.1
Oxide Applications: Dopant Barrier
Purpose: Masking material when implanting dopant into

wafer. Example: Spacer oxide used during the
implant of dopant into the source and drain regions.
Dopant barrier
spacer oxide Ion implantation
Gate
Spacer oxide protects narrow

channel from high-energy implant
Comments: Dopants diffuse into unmasked areas of silicon by

selective diffusion.
Semiconductor Manufacturing Technology Table 10.1E © 2001 by Prentice Hall
Table 10.1
Oxide Applications: Pad Oxide
Purpose: Provides stress reduction for Si3N4
Nitride Pad oxide

Passivation Layer
Bonding pad metal
ILD-5
M-4
ILD-4
M-3
Comments: Thermally grown and very thin.
Semiconductor Manufacturing Technology Table 10.1F © 2001 by Prentice Hall

Table 10.1
Oxide Applications: Implant Screen Oxide
Purpose: Sometimes referred to as “sacrificial oxide”, screen

oxide, is used to reduce implant channeling and
damage. Assists creation of shallow junctions.
Ion implantation Screen

oxide
High damage to upper Si Low damage to upper Si

surface + more channeling surface + less channeling
Comments: Thermally grown
Semiconductor Manufacturing Technology Table 10.1G © 2001 by Prentice Hall

Table 10.1
Oxide Applications: Insulating Barrier between
Metal Layers
Purpose: Serves as protective layer between metal lines.
Interlayer oxide
Passivation layer
Bonding pad metal
ILD-5
M-4
ILD-4
M-3
Comments: This oxide is not thermally grown, but is deposited.
Semiconductor Manufacturing Technology Table 10.1H © 2001 by Prentice Hall

Thermal Oxidation Growth
• Chemical Reaction for Oxidation
– Dry oxidation
– Wet oxidation
• Oxidation Growth Model
– Oxide silicon interface
• Use of chlorinated agents in oxidation
– Rate of oxide growth
– Factors affecting oxide growth
– Initial growth phase
– Selective oxidation
• LOCOS
• STI
Oxide Thickness Ranges for Various
Requirements
Semiconductor Application Typical Oxide Thickness, Å

Gate oxide (0.18 m generation) 20 – 60
Capacitor dielectrics 5 – 100
400 – 1,200
Dopant masking oxide (Varies depending on dopant, implant
energy, time & temperature)
STI Barrier Oxide 150
LOCOS Pad Oxide 200 – 500
Field oxide 2,500 – 15,000
Semiconductor Manufacturing Technology Table 10.2 © 2001 by Prentice Hall

Dry Oxidation Time (Minutes)
10.0
(100) Silicon
1.0
Oxide thickness (m)
0.1
0.01
10 102 103 104
Time (minutes)

Wet Oxygen Oxidation
Exhaust
Scrubber
Gas panel Burn box

Furnace
HCl N2 O2 H2

Consumption of Silicon during Oxidation
t 0.55t
0.45t
Before oxidation After oxidation

Liquid-State Diffusion

Charge Buildup at Si/SiO2 Interface
Silicon Oxygen
SiO2
Positive charge
Silicon

Diffusion of Oxygen Through Oxide Layer
Oxygen supplied to
reaction surface
O, O2
Oxygen-oxide
interface
SiO2
Oxide-silicon
interface
Si

Linear & Parabolic Stages for Dry
Oxidation Growth at 1100ºC
4,000 Å
Oxidation thickness
3,000 Å
2,000 Å
1,000 Å
Approximate linear region
}
100 200 300 400 500
Oxidation time (minutes)
LOCOS Process
1. Nitride deposition 2. Nitride mask & etch 3. Local oxidation of silicon

Nitride Silicon SiO2 growth
Pad oxide SiO2

(initial oxide) SiO2
Nitride
4. Nitride strip
Silicon
Cross section of LOCOS field oxide

(Actual growth of oxide is omnidirectional)

Selective Oxidation and Bird’s Beak Effect
Silicon oxynitride
Bird’s beak region
Nitride oxidation mask
Selective oxidation
Silicon dioxide
Pad oxide
Silicon substrate

STI Oxide Liner
1. Nitride deposition 2. Trench mask and etch 3. Sidewall oxidation and trench fill
Nitride Silicon Oxide over

nitride
Pad oxide
(initial oxide)
4. Oxide planarization (CMP) 5. Nitride strip Trench filled with

deposited oxide
Oxide
Sidewall liner
Silicon
Cross section of shallow

trench isolation (STI)

Furnace Equipment
• Horizontal Furnace
• Vertical Furnace
• Rapid Thermal Processor (RTP)

Horizontal and Vertical Furnaces
Performance Performance
Horizontal Furnace Vertical Furnace
Factor Objective
Typical wafer Small, for process 200 wafers/batch 100 wafers/batch
loading size flexibility
Clean room Small, to use less Larger, but has 4 process Smaller (single process
footprint space tubes tube)
Ideal for process Not capable Capable of
flexibility loading/unloading wafers
Parallel processing
during process, which
increases throughput
Gas flow Optimize for Worse due to paddle and Superior GFD and
dynamics (GFD) uniformity boat hardware. Bouyancy symmetric/uniform gas
and gravity effects cause distribution
non-uniform radial gas
distribution.
Boat rotation for Ideal condition Impossible to design Easy to include
improved film
uniformity
Temperature Ideally small Large, due to radiant Small
gradient across shadow of paddle
wafer
Particle control Minimum particles Relatively poor Improved particle control
during from top-down loading
loading/unloading scheme
Easily done in short More involved and slow Easier and quicker, leading
Quartz change
time to reduced downtime
Wafer loading Ideally automated Difficult to automate in a Easily automated with
technique successful fashion robotics
Pre-and post- Control is desirable Relatively difficult to Excellent control, with
process control of control options of either vacuum or
furnace ambient neutral ambient

Horizontal Diffusion Furnace
Photograph courtesy of International SEMATECH
Semiconductor Manufacturing Technology Photo 10.1 © 2001 by Prentice Hall

Vertical Diffusion Furnace
Photograph courtesy of International SEMATECH

Block Diagram of Vertical Furnace System
Microcontroller
Wafer handler Temperature Gas flow Boat Exhaust

controller controller controller loader controller
Quartz process chamber
Three-zone
heater
Heater 1 Gas
panel
Heater 2
Heater 3
Quartz boat
Process gas
cylinder
Wafer load/unload system

Boat motor drive system
Pressure Exhaust
controller

Vertical Furnace Process Tube
Heating jacket
Three-zone
heating
elements
Quartz tube
End cap

Heater Element Power Distribution
204 - 480 VAC 3f
Heater element
transformer
Trigger SCRs SCRs

circuit SCRs
Zone 1 Zone 2 Zone 3

Furnace heater elements
Locations of Thermocouples in the
Furnace Chamber
Thermocouple measurements
System Temperature
controller controller
Overtemperature TCs
Profile TCs
Control TCs
Heater 1
Heater 2
Heater 3
TC

Common Gases used in Furnace Processes
Gases Classifications Examples
Inert gas Argon (Ar), Nitrogen (N2)
Bulk Reducing gas Hydrogen (H2)
Oxidizing gas Oxygen (O2)
Silicon-precursor gas Silane (SiH4), dichlorosilane (DCS) or (H2SiCl2)
Dopant gas Arsine (AsH3), phosphine (PH3) Diborane (B2H6)
Specialty Reactant gas Ammonia (NH3), hydrogen chloride (HCl)
Atmospheric/purge gas Nitrogen (N2), helium (He)
Other specialty gases Tungsten hexafluoride (WF6)

Burn Box to Combust Exhaust
To facility’s
exhaust system
Wet
scrubber
Excess combustible gas burns in

hot oxygen rich chamber
Combustion chamber
(burn box or flow Filter
reactor)
O
2
O
Gas from furnace
2
process chamber
Residue
Recirculated
water

Thermal Profile of Conventional Versus
Fast Ramp Vertical Furnace
Conventional Fast Ramp
1200 1200
1000 1000
Temperature (°C)
Temperature (°C)
800 800
600 600
400 400
0 20 40 60 80 100 120 140 160 180 0 20 40 60 80 100 120 140 160 180
Time (minutes) Time (minutes)
Reprinted from the June 1996 edition of Solid State Technology,

copyright 1996 by PennWell Publishing Company.

The Main Advantages
of a Rapid Thermal Processor
• Reduced thermal budget

• Minimized dopant movement in the silicon
• Ease of clustering multiple tools
• Reduced contamination due to cold wall heating
• Cleaner ambient because of the smaller chamber
volume
• Shorter time to process a wafer (referred to as
cycle time)

Comparison of Conventional Vertical
Furnace and RTP
Vertical Furnace RTP
Batch Single-wafer
Hot wall Cold wall
Long time to heat and cool batch Short time to heat and cool wafer
Small thermal gradient across wafer Large thermal gradient across wafer
Long cycle time Short cycle time
Ambient temperature measurement Wafer temperature measurement
Issues: Issues:
Large thermal budget Temperature uniformity
Particles Minimize dopant movement
Ambient control Repeatability from wafer to wafer
Throughput
Wafer stress due to rapid heating
Absolute temperature measurement

Rapid Thermal Processor
Setpoint voltages
Heater head
Wafer Axisymmetric lamp array

Temperature
controller Pyrometer Reflector plate
Optical fibers
Feedback voltages

Rapid Thermal Processor
Photograph courtesy of Advanced Micro Devices, Applied Materials 5300 Centura RTP

RTP Applications
• Anneal of implants to remove defects and activate

and diffuse dopants
• Densification of deposited films, such as
deposited oxide layers
• Borophosphosilicate glass (BPSG) reflow
• Anneal of barrier layers, such as titanium nitride
(TiN)
• Silicide formation, such as titanium silicide
(TiSi2)
• Contact alloying

Oxidation Process
• Pre Oxidation Cleaning

– Oxidation process recipe
• Quality Measurements
• Oxidation Troubleshooting

Critical Issues for Minimizing Contamination
• Maintenance of the furnace and associated

equipment (especially quartz components)
for cleanliness
• Purity of processing chemicals
• Purity of oxidizing ambient (the source of
oxygen in the furnace)
• Wafer cleaning and handling practices

Thermal Oxidation Process Flow Chart
Oxidation Furnace
Wet Clean • O2, H2 , N2 , Cl Inspection
• Chemicals • Flow rate • Film thickness
• % solution • Exhaust • Uniformity
• Temperature • Temperature • Particles
• Time • Temperature profile • Defects
• Time

Process Recipe for Dry Oxidation Process
Process Gas
Time Temp N2
N2 O2 HCl
Step Purge Comments
(min) (ºC) Gas (slm) (slm) (sccm)
(slm)
0 850 8.0 0 0 0 Idle condition
1 5 850 8.0 0 0 Load furnace tube
Ramp Ramp temperature up
2 7.5 8.0 0 0
20ºC/min
Temperature
3 5 1000 8.0 0 0
stabilization
4 30 1000 0 2.5 67 Dry oxidation
5 30 1000 8.0 0 0 Anneal
Ramp Ramp temperature
6 30 8.0 0 0 down
-5ºC/min
7 5 850 8.0 0 0 Unload furnace tube
8 850 8.0 0 0 0 Idle
Note: gas flow units are slm (standard liters per minute) and sccm (standard cubic centimeters per minute)

Wafer Loading Pattern in Vertical Furnace
Boat size: 160 wafers
Boat pitch: 0.14 inch
Calibration parameters: Wafer size: 8 inches
Elevator speed: 9.29 cm/min
Cool down delay: 20 minutes
160
4 Filler (dummy) wafers
1 Test wafer
75 Production
wafers
1 Test wafer
75 Production
wafers
1 Test wafer
4 Filler (dummy) wafers
1
Chapter 10 Review
• Quality Measures 250

• Troubleshooting 252
• Summary 252
• Key Terms 253
• Review Questions 253
• Equipment Suppliers’ Web Sites 254
• References 255


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Semiconductor Manufacturing Technology © 2000

1. Describe an oxide film for semiconductor manufacturing,

Wafer fabrication (front-end)

Used with permission from Advanced Micro Devices

Semiconductor Manufacturing Technology Figure 10.1 © 2001 by Prentice Hall

• Nature of Oxide Film

Semiconductor Manufacturing Technology © 2001 by Prentice Hall

Used with permission from International SEMATECH

Semiconductor Manufacturing Technology Figure 10.2 © 2001 by Prentice Hall

Field oxide isolates active regions from each other.

Semiconductor Manufacturing Technology Figure 10.3 © 2001 by Prentice Hall

Semiconductor Manufacturing Technology Figure 10.4 © 2001 by Prentice Hall

Semiconductor Manufacturing Technology Figure 10.5 © 2001 by Prentice Hall

Purpose: This oxide is a contaminant and generally

Silicon dioxide (oxide)

Comments: Growth rate at room temperature is 15 per hour up

Semiconductor Manufacturing Technology Table 10.1A © 2001 by Prentice Hall

Purpose: Serves as an isolation barrier between individual

Comments: Common field oxide thickness range from 2,500 Å

Semiconductor Manufacturing Technology Table 10.1B © 2001 by Prentice Hall

Purpose: Serves as a dielectric between the gate and source-

Gate oxide Gate

Comments: Growth rate at room temperature is 15 Å per hour

Purpose: Protect active devices and silicon from follow-on

Comments: Thermally grown to several hundred Angstroms

Purpose: Masking material when implanting dopant into

Spacer oxide protects narrow

Comments: Dopants diffuse into unmasked areas of silicon by

Purpose: Provides stress reduction for Si3N4

Nitride Pad oxide

Comments: Thermally grown and very thin.

Semiconductor Manufacturing Technology Table 10.1F © 2001 by Prentice Hall

Purpose: Sometimes referred to as “sacrificial oxide”, screen

Ion implantation Screen

High damage to upper Si Low damage to upper Si

Comments: Thermally grown

Semiconductor Manufacturing Technology Table 10.1G © 2001 by Prentice Hall

Purpose: Serves as protective layer between metal lines.

Comments: This oxide is not thermally grown, but is deposited.

Semiconductor Manufacturing Technology Table 10.1H © 2001 by Prentice Hall

Semiconductor Application Typical Oxide Thickness, Å

Semiconductor Manufacturing Technology Table 10.2 © 2001 by Prentice Hall

Semiconductor Manufacturing Technology Figure 10.6 © 2001 by Prentice Hall

Gas panel Burn box

Semiconductor Manufacturing Technology Figure 10.7 © 2001 by Prentice Hall

Before oxidation After oxidation

Semiconductor Manufacturing Technology Figure 10.8 © 2001 by Prentice Hall

Semiconductor Manufacturing Technology Figure 10.9 © 2001 by Prentice Hall

Used with permission from International SEMATECH

Semiconductor Manufacturing Technology Figure 10.10 © 2001 by Prentice Hall

Used with permission from International SEMATECH

Semiconductor Manufacturing Technology Figure 10.11 © 2001 by Prentice Hall

1. Nitride deposition 2. Nitride mask & etch 3. Local oxidation of silicon

Pad oxide SiO2

Cross section of LOCOS field oxide

Semiconductor Manufacturing Technology Figure 10.13 © 2001 by Prentice Hall

Used with permission from International SEMATECH

Semiconductor Manufacturing Technology Figure 10.14 © 2001 by Prentice Hall

Nitride Silicon Oxide over

4. Oxide planarization (CMP) 5. Nitride strip Trench filled with

Cross section of shallow

Semiconductor Manufacturing Technology Figure 10.15 © 2001 by Prentice Hall