Chapter 4

Layout of MOS Transistor

- Basic MOS Transistor
-HSPICE Description of MOSFET
-Comparison of MOS Device Layout Styles
-Layout of Differential Pair
-Layout of Basic Current Mirror
-MOS Transistor Matching
*Basic NMOS Layout & Side View

Circuit Symbol

Enhancement NMOS
Physical Structure
Basic PMOS Layout & Side View

Circuit Symbol

Enhancement PMOS
Physical Structure
 MOS Transistor Matching
- Geometry effects
- Channel length modulation
- Orientation
- Diffusion and etch effect
- Contact over gate active area( threshold mismatch
- Diffusion near the channel
- PMOS versus NMOS
- PNOS exhibits 30-50% more transconductance mismatch
- Possible culprits includes increases backgate doping
variability, presence of buried channels, and orientation-
dependent stress effects.
 Thermal and Stress Effect
Oxide thickness gradients
- Stress gradients
hole, stressmax <110>, electrom, stressmax <100>
threshold voltage largely dependent on stress
- Thermal gradients
Isothermal
 MOS Devices Layout Styles

(W/L) = (W1+W2+0.6L)/L

Equivalent squares
(n=5 as shown)
(W/L) = (W1+W2+0.6L)/L
 Contact Resistance

(a) Layout (b) Equivalent circuit

 A Wide Digital Transistor Layout

(a) (b) (c)

A Wide Digital Transistor Layout
Stacked Wide Transistor (Finger Layout)
 Stacked Layout
Reduction of silicon area
Reduction of parasitic capacitance
Unmatched undercut will determine slight different
lengths
Metal lines run outside the active area to ensure
best contact of source and drain ion generator

Inner gates see the same

boundary condition Water mounted on
Low sensitive to implant tilt rotating turntable
Etch gas
mixture
Implant Tilt
 Stacked Layout
 minimize the source or drain contact area by stacking
transistors
 Respect the symmetries that exist in the electrical network
as well as in the layout ( to limit offset)
 Use low resistive path( metal, not poly) when a current
needs to be carried (to avoid parasitic voltage drop)
 Shield critical nodes (to avoid undesired node injection)
 It’s possible to enlarge, or to diminish the width of a
transistor to stack it with other transistors of the cell in a full
stacked arrangement
 benefits of reducing the parasitics
 Easier to achieve matching and to respect the electrical
symmetries
Stacked Layout

TSMC 0.25um
• The minimum channel width is
0.3um but its device is not smallest.
 Device Scaling Down
Poly
Poly
 *HSPICE Description of MOSFET
Poly

NMOS

NMOS

LD: Lateral Diffusion

LDIF: Lightly Doped Drain or Source
HDIF: LDIF edge to contact center
Source/Drain Area and Peripheral

Bottom (bulk) doping

 Diffusion Capacitance

(a) Basic MOS Structure (b) CAPACITANCE REPRESENTATION

Cd propoertional to total diffusion-
to-substrate junction capacitance
Cd=Cja ∙ (ab) + Cjp ∙ (2a+2b)
Cja: junction capacitance per um2
Cjp: peripheral capacitance per um
A: width of diffusion region (um)
b: length of diffusion region (um) (C) CAPACITANCE MODEL
 Diffusion Capacitance
Calculation of AD(AS), PD (PS), NRD(NRS)

ADeff = 2*HDIF*Weff ASeff = 2*HDIF*Weff

PDeff = 2*(2*HDIF + Weff) PSeff = 2*(2*HDIF + Weff)

 ACM = 3 (Human Work)
GEO=0: Drain and Source are not shared (default).
GEO=1: Drain is shared with another device.
GEO=2: Source is shared with another device.
GEO=3: Drain and Source are shared with another device.
Example of GEO Description (3-input NAND)
Voltage Dependent Diffusion Capacitance
 HSPICE Description of MOSFET
Mxxx nd ng ns nb mname L=length W=width
+ AD=val AS=val PD=val PS=val
+ NRD=val NRS=val M=val Geo=val

e.g.

MP1 Drain Gate Souse Bulk pmos L=0.25U W=3.60U

+ AD=1.33P AS=1.85P PD=6.56U PS=9.52U
+ NRD=0.061 NRS=0.061 M=1 GEO=0
 HSPICE Description of MOSFET
Mxxx: MOSFET element name.
nd: Drain terminal node name.
ng: Gate terminal node name.
ns: Source terminal node name
nb: Bulk terminal node name
mname: MOSFET model name
L: MOSFET channel length.
W: MOSFET channel width.
AD: Drain bottom area.
AS: Source bottom area.
PD: Peripheral of the drain junction, including the channel edge.
PS: Peripheral of the source junction, including the channel edge.
NRD: Number of squares of drain diffusion for resistance calculation.
GEO: Source/Drain sharing selector for MOSFET model.
 MOS Device Capacitance

Cgs, Cgd = gate to channel capacitance, which are lumped at source and
drain regions of channel, respectively.
Csb, Cdb= source and drain diffusion capacitance to bulk (or substrate)
Cgb=gate to bulk capacitance.

The total gate capacitance Cg=Cgb + Cgs + Cgd

 MOS Device Capacitance
1. Off region, Vgs < Vt, no channel,
Cgs = Cgd = 0
Cgb = C0 . Cdep/(Co + Cdep)

2. Linear region, Vgs – Vt > Vds

depletion region layer depth remains relatively constant,

Cgs = Cgd =

3. Saturation region, Vgs – Vt < Vds

channel heavily inverted, drain region pinch off
Cgd = 0
 Diffusion Capacitance
- As the diffusion area is reduce through sacalling, the relative
contribution of the peripheral capacitance becomes more important.
- The thickness of the depletion layer depends on the voltage across
the junction, the junction capacitance.

Where
Vj: junction voltage( negative for reverse bias)
Cjo: zero bias capacitance (Vj=0)
Vb: built-in junction potential ~ 0.6V
m: constance, depends on the distribution of impurity near the junction
m=0.3 (graded junction)
m= 0.5(abrupt junction)
MOS Device Layout Styles (example)
 Symbolic of High Speed Layout

Fig. 5. Wire capacitance associated with different transistors

Fig 2: Different N transistor in layout designs

Waffle Layout
Bent-Gate
JOGM
JOGM
Random Mismatches due to Microscopic Variation

Large device exhibit smaller mismatches ΔW/W, ΔL/L

mismatch decrease as WL increase
Random variation experience greater “averaging”
Increasing the Width to Reduce of Length Mismatch
Wide MOSFET Viewed as Parallel Narrow Device

ΔLo = statistical variation of

the length for a
transistor with ωo
Wide MOSFET Viewed as Parallel Narrow Device

μcOX and VTH suffer from less mismatch as WL increases

μcOX and VTH experience greater

AvTH and AK : proportional factor

Interdigitized Layout

BIAS
Interdigitized Layout
Interdigitized Layout
Floating Source
 Guard Ring
• p+ diffusion in p-substrate (p-well), tied to Vss
• n+ diffusion in n-well, tied to VDD
• Collect injected minority carriers
Parasitic BJT

Vertical bipolar pnp:

emitter p+, base n-well
Collector p-subtrate
 Bipolar Model
Model PNP 10 PNP 5 PNP 2
Emitter size 10*10 5*5 2*2
Base size 16*16 11*11 8*8
PNP x 9
*Layout of Differential Pair
Poor Layout with Different Orientation
 Transistor Pair Structures

Longer channel length, better matching

Matching property
(f) > (e) > (d) > (c) > (b) > (a)
Interdigitated Transistor Pair Layouts with Different Number K of Subdevices
 Transistor Pair Structures
Interdigitated Transistor Pair Layouts with
Different Number K of Subdevices
 Transistor Pair Structures

Matching property
(d) > (c) > (b) > (a)

Different common-centroid (point symmetric) Transistor pair layouts with

different number K of subdevices
Stacked Layout Effect of Gradient in a Differential Pair
Stacked Layout One-Dimentional Cross-Coupling
MOS Matching Mirror
Layout of Interdigitized Stacked Differential Pair
Layout of Interdigitized Stacked Differential Pair
Differential Pair Layout with Non-Equivalent Paracitic
Commo-Centroid Layout Differential Pair
Layout of Differential Pair
Common-Centroid Layout of Differential Pair
 Layout of Differential Pair

 Layout of differential pair showing (a) normal, (b) interdigitized, and (c) common centroid.
Layout of Differential Pair
*Layout of Basic Current Mirror Circuit
Simple Layout
 Interdigitized Type

Interdigitized Type I Interdigitized Type II

 Common Centroid Type

Common Centroid Type I Common Centroid Type II

 Gradient Modeling

VTD1 = VTD2 = VTN

1. DH : the minimum distance between D1 and D2.
2. VT1 and VT2 : the threshold voltage of two transistors with
the same W/L.
3. VTN is the threshold voltage of the reference point O which
is represented in the Fig.2(a)
Gradient Modeling (Kth segment)

Interdigitized Type I

Interdigitized Type II
Gradient Modeling (Common Centroid)
Comparison of Systematic Mismatch
Comparison in Closer Detail
Four-Segment Structure
Comparison of Three Layout Types
 Single and Double Side Layout Style

(a) (b)

“Gate Layout and Bonding Pad Struture of RF n-MOSFET for Low Noise Performance” Cheon Soo Kim
 Comparison
Compare the gate resistance of Single and Double Side Layout Style

Single-side Gate Resistance Model

REQ= 63.65Ω

Double-side Gate Resistance Model

REQ= 126Ω
 Rules for MOS Transistor Matching
1. Use identical finger geometries
- Identical channel length
- Large widths divided into section, or fingers.
- Each finger have same width and length

2. Use large active areas

- Residue offset due to random fluctuation inversely with square root of
device area.
 Rules for MOS Transistor Matching
3. For voltage matching Keep Vgst small
Two matched MOS wid same drain current

ΔVGS = ΔVt – Vgst1 (Δk/2k2)

ΔVt :difference between threshold voltages

Δk : deference between device transconductances
Vgst1 : effective gate voltage of first transistor
k2 : transconductance of second transistor

- Reduce V below 0.1V

- Large W/L ratios
- Low operating current
 Rules for MOS Transistor Matching
4. For current matching, keep Vgst large
Mismatched between drain current

ID2 /ID1 = K2 /K1 (1 + 2ΔVt /Vgst1)

-large effective gate voltage > 0.3 V

-most application cannot spare the headroom
 Rules for MOS Transistor Matching
5. Oriental transistor in the same direction
- Stress-and tilt-induced mobility variation
- Transistor lie parallel to one another
 Rules for MOS Transistor Matching
6. Place transistors in close proximity
- Gradients in temperature, stress, and oxide thickness
- Common centroid layout

7. Keep matched transistors as compact as possible

- Each devices divided into fingers, common centroid.

8. Use common centroid layout

- Even number of fingers
- Cross-coupled pair

9. Place dummy segments on the ends of array

- Equal spacing, need not same channel length
- Dummy gates connected to potential prevent channel formation
 Rules for MOS Transistor Matching
10. Place transistors in areas of low stress gradients
- Minimum in center of die
- Maximum at corners
- At least 250um away from side of die
- PMOS experience slightly less stress oriented along <100>
- NMOS always oriented horizontally and vertically

11. Place transistors well away from power devices

- More than 50mW considered as power device
- No less than 250um to 500um away from power devices
- If next to power devices, common centroid layout

12. Do not Place contacts on top of active gate area

- Place gate contact over thick field oxide
- Minimum number and size of gate contacts
- Place them in the same location on each transistor
 Rules for MOS Transistor Matching
13. Do not route metal across active gate region
- Dummy leads added to every section of array
- Identical length of lead

14. Keep all junction of deep diffusion far away from active gate area
- Minimum spacing between a well boundary and matched transistors , at
least twice the well junction depth.

15. Place precisely transistors on axes of symmetry of die

- If large number of matched transistor, serve the optimal location for the
most critical devices.
 Rules for MOS Transistor Matching
16. Do not allow N+ buried layer shadow to intersect active gate
area
- If NBL shift is known, allow adequate overlap of NBL over the
transistor on all sides.
- If NBL shift is unknown, overlap of NBL at least 150% of maximum
epi thickness.

17. Connect gate fingers using metal straps.

- Simplify the connection of gate electrodes.

18. Use thin-oxide devices in preference to thick-oxide devices.

- For process with multiple-thickness of gate oxide
- Thinner gate oxide, better matching

19. Consider NMOS transistor rather than PMOS transistors.