Retention Based Low Power DV

Challenges in DDR Systems

Subhash Joshi, Sangaiyah Pandithurai ,
Halavarthi Math Revana Siddesh
Qualcomm, Bangalore, India

© Accellera Systems Initiative 1

 Agenda
• DDR System Overview
• Low Power Techniques & Verification scope
• DV Challenges for DDR Systems
• DV Strategies for DDR Systems
• Return on Investment [ROI]
• Conclusions
• Q&A

© Accellera Systems Initiative 2

 DDR System structure
• Multiple clients requesting DDR Band-Width
• Frequency Bump, Increasing complexity, Phy & MC
• Performance requirements and power budget
• Shrinking technologies & LP techniques
• Multiple PD, MC & DDR-PHY on-off combinations
Client-0
DDR A
Client-1 Arbiter/ DDR DDR B
Scheduler DD MC PHY DDR C
Client-2
DDR D
Client-N
Multiple Masters Requesting DDR BW

© Accellera Systems Initiative 3

 Low Power Techniques
Power Saving:- Active->LP->Partial ON Switches

Software based SAVE-RESTORE

• Slow wake-up time
• Latency proportional to design config. Space
• Important regs in config space.

Flop retention based SAVE-RESTORE

• Retention flops/Special low leakage flops
• Fast wake-up time
• Regs in Config space and Non config space.

© Accellera Systems Initiative 4

 LP Verification Scope
• Power Architecture
– Power domains - Power modes - Multi-voltage -Isolation
strategies & LP Techniques.
• Power-Intent spec(UPF) correctness
• Power-Domain interactions
• Isolation strategies.
• LP Techniques & Design Integrity (PVM)
– Power verification Matrix
System Scenarios
Matrix
Functional Performance Security Clock- Gating Multiple-PD
Power √ √ √ √ √

© Accellera Systems Initiative 5

 DV Challenges for DDR System
• Brand-New Design & Retention Space

Config Non- Config

Space Space
Retention Space

• DDR-System or timing/Control Intensive Designs

• Retention Miss/State-space elements END LESS
• Incorrect flop in Retention CHALLENGES

• Coverage Convergence & Sign-off

• Ensure Retention list completeness

© Accellera Systems Initiative 6

DV Strategies for DDR System
PVM Compliant Feedback DV Func, Perf,
Test-Plan Vectors Security, Power.

Scenario Gen. & Injection Assert Checks &

Checks Timestamp Capping Bins

Methodology Exploring CAD Regress Opt &

Excellence Tools Cov. Extraction

Functional & Complex &

Timelines
Power in Huge debug
alignment
Parallel space

© Accellera Systems Initiative 7

 DV Strategies Cont.…....
Phased Approach
Phase I [BRING-UP]
• UPF Clean-up, Behavioral power-models and CAD Tool environments.
• Config space retention, isolation-values & Data-path scenario.

Phase II [ FEATURE- DIRECTED ]

• Design Feature focused.
• Assertion checks and Functional Coverage model updates.

Phase III [RANDOM]

• All features enabled and disabled randomly
• Multiple PC , Frequencies Sweep & DDR Aware traffic

© Accellera Systems Initiative 8

 DV Strategies Cont.…..
• Example approach to target Retention space

Check Reg
Write IsolationEN Check Iso Power
Power on Reset Content &
Config Reg Initiate_PC Values Restore
Iso values

Simplified power collapse sequence and configuration space retention verification scheme

I
Config Non- Config Always-ON
S
Space Space O
Domain
Retention Space

Functional Performance Power TP Firewall-

TP TP Multiple-PD Security TP
Non- configuration space retention verification scheme

© Accellera Systems Initiative 9

 ROI
Strategic
Processes
Better Returns
Power

Performance

Functional

Security

© Accellera Systems Initiative 10

 ROI Cont.……
Functional

State space to DDR Device Type

DRAM De-rating
save FSM states or change post
feature
Device state collapse.

Information
Scenario time-
exchange across
stamp is
multiple
important
Hierarchy.

Scenario Injected post –collapse X

Inject scenario -> PC -> Verify/Check √
© Accellera Systems Initiative 11
 ROI Cont.……

Performance
Security
( Un-noticeable or Silent bugs)

Long-Lived Momentary
Crypto or
Performance Performance
Firewall
Impact Impact

PERF Power PERF REGAIN

Power-up Event (E_A) SETTINGS Collapse & Event (E_A)
Restore Degradation PERF_A
(PERF_A)

© Accellera Systems Initiative 12

 ROI Cont.……

Clock-Gating/ Lock/MC to Identifying MISC

Dynamic Pwr Phy interface SW • Power intent
• Dual handshake workarounds checks,
• Un-gated Clocks
to DDR – No
and power upfront • Multiple PD’s
down with • Isolation
functional but • Late in the show
active miss/Level
power issue. • Difficult fix &
handshake shifters: Static
Product life checks
cycle
dependency

© Accellera Systems Initiative 13

 Sign-off & Re-use
Coverage Convergence & Sign-off
• Leverage Functional verification Infrastructure
• Readily available assertion & coverage checks
• Automatic. Coverage model for Retention list
• N flops , Analyzing each flop - state retention of 1 or 0

LP techniques interchangeable usage

• Config vs Retention

© Accellera Systems Initiative 14

 Conclusion
Complex Control Intensive designs are
dreadful to crack
Swing around PVM
compliant test-plan
Focus on Test-planning & Perfect
execution rather PA bring-up
Key to Success:- Planning functional
& Power Aware in ||
ENDLESS CHALLENGES mandate
SMART STRATEGIES to witness high ROI

© Accellera Systems Initiative 15

 Q&A

© Accellera Systems Initiative 16