Input Output Organisation: BY: Vaishakh B N USN:1RV09CS1114

INPUT OUTPUT
ORGANISATION
BY: Vaishakh B N
USN:1RV09CS1114
CONTENTS
1)Accessing Input output

Devices
2)Interrupts
INTRODUCTION
ACCESSING I/O DEVICES
Processor Memory
Bus
I/O device 1 I/O device n
A simple arrangement of connecting I/O devices using a single bus is shown in the
above figure.
The bus consists of 3 sets of lines
1)Address lines
2)Data lines
3)Control lines
Since there is a common bus, if more than one device is enabled at a time , the data
on the bus will be ambiguous and results in a problem called “BUS CONTENTION”
To avoid this condition each i/o device is assigned a unique address. Only the
addressed device is enabled and responds to the commands issued by the control
lines
MEMORY MAPPED I/0 (1/2)
Memory mapped I/O is one of the ways to deal with I/O
devices. In this case the memory and the I/o devices
share a common address space.
The most significant bit (MSB) of the address bus is
used to differentiate I/O and memory.
We normally associate a buffer (analogous to
memory) with each I/O device.
Since I/O is also used as memory, any data transfer
instruction like Move, Load can be used to exchange
information.
EX: If DATAIN is the input buffer associated with the
keyboard, then the instruction
Move DATAIN, R0
reads the data from DATAIN (key value stored in buffer
)and stores it to process register R0.
MEMORY MAPPED I/O (2/2)
Similarly the instruction
Move R0, DATAOUT
Sends the contents of register R0 to the location
DATAOUT, where DATAOUT is the name of the output
data buffer of a display unit or a printer.
 DISADVANTAGES:
 Generally, the number of I/O devices in a system are
not large. Hence, this scheme results in insufficient
utilization of large address space provided to the I/O
devices
Since instructions are same for both memory and I/O
devices , the programmer has to be cautious to decide
whether the data transfer is with I/O or memory.
Also decoding the circuitry is complex.
I/O MAPPED I/O
Memory and I/O address space are different.
IN and OUT special instructions are used for data
transfer.
The advantage of separate I/O space is that I/O
devices deal with lesser address lines resulting in
small decoder size and simpler hardware.
Separate I/O address space does not necessitise
separate address lines on the processor bus. A
special signal on the bus indicates whether the sent
address is from memory or I/O device.
In order to have an efficient and organized data
transfer, an intermediary is required between the
processor and I/O devices. This is called I/O
interface .
I/O INTERFACE
Address lines
BUS
Data lines
Control lines
I/O Interface
Address Control Data and
Decoder Circuits Status Registers
Input Device
INTERFACING I/O DEVICES
Three mechanisms have been developed for
interfacing I/O devices.
Program Controlled I/O
Interrupt I/O
Hardware controlled I/O
PROGRAM CONTROLLED I/O
Consider an example of interfacing of keyboard and display to
the CPU
We have SIN associated with keyboard
SOUT associated with display
SIN=1 indicates that character is entered at the keyboard.
Once the processor reads the character, SIN becomes 0
Similarly SOUT=0 indicates that the display is busy and when
SOUT is 1 the display is ready to receive a character.
In Program Controlled I/O the processor repeatedly checks a
status flag to achieve synchronization with an I/O device, for
data transfer. This is called “POLLING ” of the device.
This method has a drawback that that it wastes the time by
checking the status of the device before the actual data
transfer.
Input/Output Organization
4.1 Accessing I/O Devices -Registers in
Keyboard and Display interfaces
DATAIN
DATAOUT
STATUS DIRQ KIRQ SOUT SIN
CONTROL DEN KEN
7 6 5 4 3 2 1 0
Accessing I/O Devices - I/O Program with
Keyboard and Display
 Move #Line,R0 %Initialize memory

pointer
 WAITK: TestBit #0,STATUS %Test SIN
 Branch>0 WAITK %Wait for character to be entered
 Move DATAIN,R1 %Read Character
 WAITD: TestBit #1,STATUS %Test SOUT
 Branch=0 WAITD %Wait for display to
become %ready
 Move R1,DATAOUT %Send Character to
display
 Move R1,(R0)+ %Store character and
%advance pointer
 Compare #$0D,R1 %check if carriage
return
 Branch≠0 WAITK %If not, get another
character
 Move #$0A,DATAOUT%Otherwise send linefeed
 Call PROCESS %Call a subroutine to
process %the input line
INTERRUPTS
In this method the I/O device initiates the action instead
of the processor. This is done by sending a hardware
signal called as interrupt request line.
 The processor can be performing its own task without
the need to continuously check the I/O device. When the
device gets ready, it will “alert ” the processor by
sending an “interrupt”
INTERRUPT I/O
 It is similar to subroutines(chapter 2)
 The routine executed in response to an interrupt is called the
INTERRUPT SERVICE ROUTINE
 In our example PRINT routine is the ISR. The interrupt request
comes from the execution of instruction i as shown in figure.
Print Routine
Compute Routine
1
2
. .
. .
Interrupt .
i
Occurs .
i+1 .
here
.
M
Input / Output Organization
Interrupts
 Assuming arriving of interrupt during
execution of ith instruction in Compute routine
following action will be taking place.
1. Processor completes execution of ith

instruction in compute routine.
2. Current Program Counter of Compute

(address of (i+1)th instruction) is saved by
processor on stack
Interrupts
3. Current status processor i.e. Processor
Status Word ( condition code flags etc.) is
saved on stack.
4. Program counter is loaded with 1st
instruction of Print interrupt service routine.
5. Interrupt routine is executed
6. At the end of Interrupt service routine (on
Return from Interrupt), the PSW from stack
is restored from stack .
7. PC of Compute is restored from stack.
Interrupts - Interrupt Hardware
 An equivalent circuit for an open-drain bus used to
implement a common interrupt-request line Vdd
Processor
R
INTR
INTR O
......
INTR1 INTR2 INTRn

 I/O Device requests an interrupt by activating a bus
line called interrupt-request.
 Computers may have several I/O devices that can
request an interrupt.
 A single interrupt line may be used to serve n
devices.
 All devices are connected to the line (Control Line)
via switches to the ground.
 To request an interrupt, a device closes its

associated switch. Vdd
Processor R
O IN
T ......
R
INT INT INT
 If all Interrupt signals INTR1 to INTRn are inactive,
that is if all switches are open, the voltage on the
interrupt-request line will be equal to Vdd.
 This is inactive state of line ( no interrupt
O request
I
is pending) ......
 When a device requests an interrupt by closing its
switch, the voltage on the line drops to 0, causing
the interrupt-request signal, INTR, received by the
processor to go to 1.
 Closing of one or more switches will cause the line
voltage to drop to 0, the value of INTR is the
logical OR of the requests from individual devices.
 In the electronic implementation of circuit, special gates
known as open-collector (for bipolar circuits) or Open-drain
(for MOS circuits) are used to drive INTR Line.
 The output of an open –collector or open-drain gate is

equivalent to a switch to ground that is open when gates
input is in the 0 state and closed when it is in the 1 state.
 The voltage level, hence the logic state, at the output of
the gate is determined by the data applied to all the gates
connected to the bus, according to the equation
 INTR = INTR1 + INTR2 + . . . . . + INTRn
 Resistor R is called a pull-up resistor because it pulls the

line voltage to the high-voltage state when the switches
are open.
Input/Output Organization Interrupts -
Enabling and Disabling Interrupts
 The interrupt facility provided in the computer must
give programmer complete control over the events
that takes place during program execution.
 The arrival of Interrupt from an external device
causes processor to suspend execution of one
program and start the execution of another.
 Because interrupts may arrive at any time,
interrupts may alter the sequence of events from
that envisaged by the programmer.
 Hence, interruption of program execution must be
carefully controlled.
 Such facility is enabling and disabling of interrupts
as desired.
Interrupts - Enabling and Disabling Interrupts
 When a device activates the interrupt-request signal,
it keeps this signal activated until it learns that
processor has accepted its request.
 Interrupt-request signal will be active during the

execution of interrupt-service routine, until an
instruction is reached that accesses the device in
question.
 It is essential to ensure that this active request

signal does not lead to successive interruptions,
causing the system to enter an infinite loop from
which it can not recover.
Interrupts - Enabling and Disabling
Interrupts – 1st Option
 First option is processor hardware to ignore (do not disable)
interrupt-request line until the execution of 1st instruction in
interrupt service routine.
 After entering interrupt service routine,1st executable

instruction in interrupt service routine may be execution
Disable Interrupt instruction.
 By DI, programmer is ensured that no repeated interruptions
will not occur until Enable interrupt instruction is executed.
 Enable Interrupt instruction is executed as the last
instruction in Interrupt Service Routine before the execution
of Return-from-Interrupt instruction.
Interrupts –2nd Option
 Second option is suitable for a simple processor with
only one interrupt request line, is to have the
processor automatically disable interrupts before
starting the execution of interrupt service routine.
 After saving PC and PSW on the stack, processor
performs the equivalent of Interrupt-Disable
instruction. Interrupt Enable bit is often one bit in
Processor-Status-Word.
 When a Return-From-Interrupt instruction is
executed at the end of ISR, the contents of PSW and
PC are restored from the stack and interrupt is
enabled by setting the IE bit in PSW.
Interrupts –3rd Option
 Third option is, processor has a special interrupt-request
signal line for which interrupt-handling circuit responds to
the leading edge of the signal.
 Such line is said to be edge-triggered.
 In this case, processor will receive only one request

regardless of how long the line is activated.
Interrupts – Typical Scenario
 The device raises an interrupt request
 Processor interrupts the program currently executed.
 Interrupts are disabled by changing control bits in the
PSW (except in the case of edge-triggered interrupts)
 The device is informed that its request has been
recognized, and in response, it deactivates the interrupt-
request signal.
 The action requested by the interrupt is performed by the
Interrupt-Service-Routine.
 Interrupts are enables and execution of the interrupted
program is resumed.
Interrupts - Handling Multiple devices.
 In case of processor being connected to multiple devices capable

of initiating interrupts, there is no definite order in which they
will generate interrupts.
 Because these devices are optionally independent a device
may request an interrupt while another is being serviced or
several devices may request interrupts exactly at the same
time.
 This gives rise to number of questions to be answered.

 How can the processor recognize the device

requesting an interrupt?
 Given that different devices are likely to require
different Interrupt-Service-Routines, how can the
processor obtain/know the starting address of the
appropriate routine in each case?
 Should a device be allowed to interrupt the processor
while another interrupt is being serviced?
 How two or more simultaneous interrupt request be
handled.
 The information needed to determine the device
requesting interrupt is available in Status
register through the bit IRQ for each device.
 One way is to pole the IRQ bits and determine
the device and service the interrupt.
 If multiple devices interrupts, pole one after the
other the IRQs and service requests by executing
appropriate Service routine for that device.
 Polling scheme is easy to implement, but main
disadvantage is time spent interrogating the IRQ
bits of all devices in an order.
 Alternatively, most common and efficient is
vectored interrupts.
Interrupts - Handling Multiple devices –
Vectored Interrupts
 A device requesting interrupt can identify itself by
sending a special code to the processor over the bus.
 This enables processor to identify individual devices
even if they share a single Interrupt-Request line.
 Code length is typically in the range of 4 to 8 bits. This
code identifies the vector address (memory location) of
that device wherein the processor/Interrupt handler can
find address of Interrupt Service Routine of that device.
 The processor reads the address of the ISR from the
Interrupt vector of the interrupted device and loads into
PC for ISR execution to start.
 The Interrupt vector may also include a new value for
the Processor status Register (PSW)
Vectored Interrupts
 In Most computers, I/O devices send the interrupt-vector code
over the data bus using the bus control signals to ensure that
devices do not interfere with each other.
 When a device interrupts processor may not be ready to
honor/take the request and vector code immediately.
1. First processor has to complete the current instruction under execution.
2. Interrupt might be disabled at the time the request is raised.
 The interrupting device must wait to put data on the bus until
the processor is ready to receive it.
 When the processor is ready to receive the interrupt-vector
code, it activates Interrupt-Acknowledge line, INTA.
 The I/O device responds by sending its interrupt-vector code
and turning off the INTR signal.
Vectored Interrupts – Interrupt nesting
 Interrupts may be disabled during the execution of
Interrupt service routine so that repeated interrupts from
the same device do not occur continuously.
 The same may be used for when several devices are
involved.
 This ensures that once the execution of ISR is started, it
always continues to completion before processor accepts
an interrupt request from another device or same device.
 Interrupt service routine are/shall be short, and the delay
they may cause is acceptable for all simple devices.
Vectored Interrupts – Interrupt nesting
 However, for some devices a long (relative) delay in
responding to Interrupt request may lead to erroneous
results.
 Example :
 Real-time clock or System Clock:
 This device sends interrupt requests at regular intervals,
for each of which processor executes a small program
(ISR) to update counters in the memory to keep track of
second, minutes, and so on.
 A proper operation requires that the delay in
responding to an interrupt request from real-time clock
be small in comparison with the interval between two
successive requests of Real-time /System Clock
requests.
Vectored Interrupts – Interrupt nesting – device
priority
 To ensure the requirement of responding to some
requests immediately (relative qualification), it is
necessary to accept an interrupt request during the
execution of an Interrupt-Service routine for another
device.
 This leads to the requirement that I/O devices shall
be organized in a priority structure.
 This brings the situation or a rule to honor interrupt
requests from higher-priority devices while processor
is servicing another request from lower priority
device than the interrupting device.
Vectored Interrupts – Interrupt nesting – Processor
priority
 Multiple level priority organization means that during the
execution of an Interrupt service routine, interrupt requests
will be accepted from some devices based on their priority
and the current priority.
 To implement this scheme, there shall be a provision to
assign a priority level to the processor that can be changed
under program control.
 The priority level of the processor is the priority level of the
program that is currently being executed.
 Finally it can be stated that the processor accepts interrupts
only from the devices that have priorities higher than its own.
priority in PS
 At the time of execution of an ISR for some device
is started, the priority of the processor is raised that
device so that,
 This action disables (logically), interrupts from devices at
the same level of priority or lower.
 However interrupt requests from higher priority devices
will continue to be accepted.
 Processor priority is usually encoded in a few bits of
the processor status word.
 The processor priority can be changed by program
instructions that write into the PS.
 The instructions which can change processor priority are
called privileged instructions, which can be executed
when processor is running in supervisor mode.
priority in PS
 At the time of execution of an ISR for some device is
started, the priority of the processor is raised that
device so that,
 This action disables (logically), interrupts from

devices at the same level of priority or lower.
 However interrupt requests from higher priority

devices will continue to be accepted.
priority in PS – Privileged Instructions –Supervisor
Mode.
 Processor priority is usually encoded in a few bits
of the processor status word.
 The processor priority can be changed by

program instructions that write into the PS.
 The instructions which can change processor

priority are called privileged instructions,
which can be executed when processor is
running in supervisor mode.
priority in PS – Privileged Instructions –Supervisor
Mode.
 Processor will be in supervisor’s mode only when
executing Operating System Routines.
 It switches to user mode before beginning to execute
application programs.
 This ensures that, a user program cannot accidentally
or intentionally, change the priority of the processor
and disrupt the system operation.
 An attempt to execute a privileged instruction in
while in user mode leads to a special type interrupt
called privilege exception.
priority – Priority arbitration
 Multiple priority scheme can be implemented using separate
interrupt-request (IR) and interrupt-acknowledge (IA) lines for each
device.
 Each of the IR lines is assigned s different priority level.
 Interrupt requests received over these lines are sent to a priority
arbitration circuit in the processor.
 A request is accepted only if it has higher priority level than that
currently assigned to the processor.
Interrupts - Handling of Multiple devices
 Implementation of interrupt priority using individual
interrupt request and acknowledge lines.
INTR1 INTR2 INTRp

Processor
Device 1 Device 2 ... Device p
INTAp
INTA1 INTA2
Priority arbitration
Circuit
priority – Simultaneous requests
 Simultaneous requests
 When simultaneous requests are to be handled from two
or more devices of the same type, processor must have
means of deciding which request to service first.
 In this case several devices share one interrupt-request
line.
 Polling status registers of such devices is simple, priority
is determined by the order of polling.
 When vector interrupts are used, it must be ensured that
only one device is selected to send its interrupt vector.
 A widely used mechanism of connecting devices of
the same type or sharing one Interrupt-request line is
to connect them in daisy chain.
 Interrupt request line (INTR) is common to all the
devices.
 Interrupt acknowledge line (INTA) is connected in a
daisy-chain fashion, such that the INTA signal
propagates serially through the devices.
 When several devices raise an Interrupt-request and
the INTR line is activated.
 The processor sends INTA line to device 1.
 The signal (INTA) received by device 1 is passed to
next device in the chain only if it does not require
service.
 If Device 1’s request is pending, it blocks INTA signal
and proceeds to its identification by putting its code
on the data bus.
 In this daisy chain arrangement the device which is
closer to the processor has highest priority.
 Interrupt Priority Schemes – Daisy Chain
INTR
Processor
….
Device 1 Device 2 Device n
INTA
 More general structure of connecting/handling devices is
 To organize devices in groups, and each group is connected
at a different priority level.
 Within a group, devices are connected in a daisy chain.
 Interrupt Priority Schemes – Arrangement of priority Groups
INTR 1
Device Device
INTA 1
Processor
. .
INTR p . .
Device Device
INTA p
Priority arbitration
circuit
Interrupts - Controlling Device requests
 It is important to ensure that interrupt-requests are

generated only by those I/O devices that are being
used by a given program.
 Or Idle devices shall not be allowed to generate
interrupts even though they are ready to participate
in I/O transfer.
 This is being achieved by Interrupt-Enable control bit
in the device Interface Register.
 Device shall not raise the Interrupt-Request if
Interrupt enable control bit in the device register is
cleared.
 Example: DEN & KEN for display unit and Keyboard
in control register of the Interface.
Interrupts - Controlling Device requests –
Interrupt Enable at Device End and Processor End
 The two independent mechanisms for controlling interrupt-

request are:
1. At the device end, an interrupt-enable bit in a control
register determines whether the device is allowed to
generate an interrupt-request.
2. At the processor end, either interrupt-enable bit in PS
register or a priority structure determines whether a
given request will be accepted.
Initialization of Interrupt
 Assuming that at some point in a main program an input
line is required to be read from the keyboard and store
characters in successive byte locations in the memory
starting at a location Line.
 To perform this operation using interrupts, it is required

to initialize interrupt process.
Initialization of Interrupt
 Initialization of Interrupt
 Load the starting address of the Interrupt-Service-

Routine (ISR) in location INTVEC
 Load the address LINE in a memory location PNTR.
The Interrupt-Service-Routine will use this location as
a pointer to store the input characters in the memory.
 Enable keyboard interrupts by setting bit 2 in register
CONTROL to 1.
 Enable Interrupts in the processor by setting to 1 the
IE bit in the processor status, PS.
Interrupt Service Routine (ISR)
 Interrupt Service Routine (ISR)
 Read the input character from the key board
input data register. This will cause the interface
circuit to remove its interrupt request.
 Store the character in memory location pointed
to by PNTR, and increment PNTR.
 When end-of-line is reached, disable keyboard
interrupts and inform program main.
 Return-From-Interrupt.
Programs: Interrupt Service Routine (ISR) - Main
 Main Program
 Move#LINE,PNTR %Initialize buffer Pointer
 Clear EOL %Clear end-of-line indicator
 BitSet #2,CONTROL %Enable Keyboard interrupts.
 BitSet #9,PS %Set Interrupt-Enable bit in the PS
 .
 .
Programs: Interrupt Service Routine (ISR) - Main
 Interrupt-Service Routine
 Read: MoveMultiple R0-R1,-(SP) %Save R0 and R1 on the
%stack
 Move PNTR,R0 %Load address pointer
 MoveByte DATAIN,R1 %get in put character and
%store in R1
 MoveByte R1, (R0)+ %Store character in memory
 Move R0,PNTR %Update pointer
 CompareByte #$0D,R1 %check if carriage Return
 Branch≠0 RTRN %
 Move #1,EOL %Indicate end of Line
 BitClear#2,CONTROL %Disable Keyboard interrupts.
 RTRN: MoveMultiple (SP)+,R0-R1 %Restore R0 and R1 from the
%stack
 Return-from-interrupt
Interrupts - Exceptions
 An exception is often used to refer to any event that
causes an interruption to the execution of a
program.
 I/O Interrupts are one type of exceptions.
 Recovery from Events:
 Computers use a variety of techniques to ensure all
hardware components are operating properly.
 Example:
 Computer may include an error-checking code to the
main memory, which allows detection of errors in the
stored data.
 If error occurs, the control hardware detects it and
inform the processor by raising an interrupt
 Example:
 The processor may also interrupt a program if it
detects an error or an unusual condition while
executing the instructions of this program.
 Like the OP-code field of an instruction may not
correspond to any legal instruction (illegal
instruction)
 An arithmetic instruction may attempt a division by
zero.
 A privileged instruction is attempted to be executed
in user mode.
 In a program instruction the operand may point to an
unavailable memory.
 When exception occurs and processing is
initiated as a result of such errors, the processor
proceeds exactly the same manner as in the
case of and I/O interrupt request.
 It suspends the program being executed and
starts an exception-service-routine. This takes
appropriate action to recover from the error, if
possible, or to inform the user about it.
 Unlike I/O interrupt, when an exception is caused
by an error, execution of the interrupted
instruction cannot be completed and processor
starts exception process immediately.
Interrupts - Exceptions - Debugging
 Another important type of exception is used as an
aid in debugging programs (debugger), which is
System software program.
 The debugger uses exceptions to provide two
important facilities called trace and breakpoints.
 When a processor is operating in the trace mode, an
exception occurs after execution of every instruction,
using the debugging program as the exception-
service-routine. Trace exception is disabled during
the execution of debugging program.
 Break points provide a similar facility, except that
the program being debugged is interrupted only at
specific points selected by user.
Interrupts - Exceptions – Debugging-
Software Interrupt or Trap
 An Instruction called Trap or Software-Interrupt is
usually provided for this purpose.
 Execution of this instruction results exactly the

same actions as when a hardware interrupt
request is received.
 While debugging a program (using Debugger)
user may want to break at the instruction i, then
debugger saves instruction at i+1 and replaces it
with a software interrupt instruction and makes
the debugger program as the exception handling
service routine or rap service routine.
Interrupts - Exceptions – Debugging-
Software Interrupt or Trap
 When program is executed and reaches that point (instruction
i+1), it is interrupted and the debugging routine is activated.
 This gives a chance for user to examine memory contents and
register contents with the help of debugger.
 When the user is ready to execute the program further the
saved instruction is replaced at location i+1.
Interrupts - Exceptions – Privilege Exception
 To protect operating system from being corrupted by user
program, certain instructions can be executed only in
supervisor mode.
 These instructions are called Privileged Instructions.
 Example: when system is executing in user mode the
program is not allowed to execute instructions to change
priority of the processor, or that enables a user program to
access areas in the computer memory that have been
allocated to other users.
 An attempt to execute such instructions will produce
privilege exception, causing the processor to switch to the
supervisor mode and begin executing appropriate routine in
the operating system.

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INPUT OUTPUT

1)Accessing Input output

I/O device 1 I/O device n

STATUS DIRQ KIRQ SOUT SIN

CONTROL DEN KEN

 Move #Line,R0 %Initialize memory

1. Processor completes execution of ith

2. Current Program Counter of Compute

INTR1 INTR2 INTRn

 To request an interrupt, a device closes its

 The output of an open –collector or open-drain gate is

 INTR = INTR1 + INTR2 + . . . . . + INTRn

 Resistor R is called a pull-up resistor because it pulls the

 Interrupt-request signal will be active during the

 It is essential to ensure that this active request

 After entering interrupt service routine,1st executable

 Such line is said to be edge-triggered.

 In this case, processor will receive only one request

 In case of processor being connected to multiple devices capable

 This gives rise to number of questions to be answered.

 How can the processor recognize the device

 This action disables (logically), interrupts from

 However interrupt requests from higher priority

 The processor priority can be changed by

 The instructions which can change processor

INTR1 INTR2 INTRp

Device 1 Device 2 ... Device p

 It is important to ensure that interrupt-requests are

 The two independent mechanisms for controlling interrupt-

 To perform this operation using interrupts, it is required

 Load the starting address of the Interrupt-Service-

 Execution of this instruction results exactly the

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