Status report on FLEX design

A. Brogna, A. Kurt, L. Masetti, M. Robles

HGTD modules assembly meeting
October 1st, 2018
FLEX cable
• The prototype produced by Schoeller Electronics is finally in Mainz:
• 8 pieces of the longest FLEX (750 mm): 2 out of them assembled in a
company. Rest of pieces in house.
• 8 pieces of the medium FLEX (435 mm). They are assembled in house.
• 25 small pieces for glue and stave loading testing.

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FLEX testing

• Testing has started:

• Geometrical test to check the
geometrical requirements
• HV insulation Flex
cable

• The adapter board is in house and

Adapter board
it was assembled by a company.
• Test bench (Kintex + Adapter
board) for IBERT test and power
integrity test ready.

• First test at room temperature Kintex

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FLEX connector
• Glenair (UK) was contacted to customize a connector for the FLEX and the peripheral electronics.
• Number of signals/pins per module
Signal type Signal name No. of wires Comments
HV 1 kV max. 2 Clearance
POWER 1x Vdda, 1x Vddd 2 Minimise voltage drop
GROUND Analog, Digital 1 plane Dedicated layer
Slow control Data, Ck (opt. +rst, error) 2 to 4 I2C link
Input clocks 320 MHz, Fast command e-link 4 or 8 CLPS
(opt. 40 MHz(L1))
Data out lines Readout data (TOT, TOA, Lumi) 4 pairs 4 e-links differential CLPS
ASIC reset ASIC_rst 1 Digital
Monitoring Temperature, Vdda, Vddd 1 or 3 DC voltage

• Nathalie, electronics meeting: To be checked with the LpGBT designers

• Cmd_pulser/cmdb_pulser: in fast command elink?
• 320 MHz and fast cmd elinks: shared by 2 ASICs or more
• Do we need the 40 MHz elink? Cf Ramon
• Number of wires for the monitoring: only one.
• Number of pins: 40-50 pins
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FLEX “geometrical” design
• A proposal for the peripheral electronics during the TDR meeting
implies that some of the FLEXes might be “bent” in the XY plane.
• This should not affect the perfomance of the FLEX in terms of High-
Speed transmisión but it could lead to ploblems when
manufacturing the FLEX. It would be more convenient to have a
design bent 45-90, but the dimensions of the panel production
must be checked in order to know if the longest FLEXes can be
manufactured.

Peripheral board

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Backup slides

6
Test implementation

• Post layout simulations with Cadence “Sigrity” and “PowerSI” (signal integrity
and power distribution over long lines).
• Test plan with Kintex KC705. An adapter board is under development as plug-
in for the FMC High-Speed connector on the KC705.
• The FPGA is programmed to inject test patterns at 1.25Gbps and check the
response with the IBERT. SMA connectors on the adapter board route the
signals to the oscilloscope for classical eye-diagram analysis.
• The I/O drivers in the KC705 are compatible with the VC707 used by the
LpGBT designers. Test conditions close to the on-field operation.
• The insulation of the FLEX materials is checked up to 1 kV by the insulation
tester Megger MIT430. The IBERT will be tested w/wo HV in order to test the
feasibility of keeping the HV line in the FLEX.

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Schematic drawing of two adjacent modules on the top side and one on the
bottom side of the cooling plate; the modules are mounted on thin support plates