Low Power VLSI Design:

Challenges and solutions

Dr.S.Saravanan M.E.,PhD
HOD/EEE(UG)
Muthayammal Engineering College
Rasipuram

12.03.2012 1
Agenda
Motivation
Introduction To VLSI design
Sources of Power Dissipation
Low Power Design Methodologies
Low Power Soc Designs
Low Power Multiplier Design
Design of Low Power MAC
Conclusions

12.03.2012 2
Motivation

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 Motivation
PORTABLE DEVICES …….Note Book Computers,
PDAs, Laptops, Cell Phones, Pacemaker etc historical
drivers of low power ……..require low power
consumption & high through put

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 Motivation (Contd..)
• New portable compute-intensive applications
* Multi-media
* Video display and capture
* Audio reproduction & capture
* Handwriting recognition
* Notebook computer
* Personal data assistant
* Implantable medical electronics

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Motivation (contd..)
Why so much of stress on Low Power?
Portable devices run on battery
Battery life is limited
Energy density of Nickel-Metal Hydride
(NiMH) is low@30Wh/lb
The battery technology is not improving at the
same speed as that of VLSI

12.03.2012 6
VLSI Chip Power Density
10000 Sun’s
Surface
Rocket
Power Density (W/cm2)

1000
Nozzle
Nuclear
100 Reactor

Hot Plate
8086
10 4004 P6
8008 8085 386 Pentium®
286 486
8080
1
1970 1980 1990 2000 2010
Year
12.03.2012 7
Motivation (contd..)
Power dissipation increases with the increase
in clock speed
This will increase the cost packaging to
remove the heat
Increased Power will generate excessive heat.
This will cause Electro migration
Thus Reliability becomes an added issue to
cost

12.03.2012 8
 Agenda
Motivation
Introduction To VLSI Design
Sources Of Power Dissipation
Low Power Design Methodologies
Low Power Soc Designs
Low Power Multiplier Design
Design of Low Power MAC
Conclusion

12.03.2012 9
 What is Micro
Electronics?
he size of the Electronic Devices in
μ- Electronics is in the range of micromet

• Examples.. ICs……..

• μ- Electronics gave ICs

• Advantages of such devices…..

12.03.2012 10
 Some Land Marks
• 1883 - Thomas Alva Edison , demonstrated the conduction
of electrons in vacuum
• 1904 - John Fleming invented the vacuum diode
• 1947 – The transistor was developed by BARDEEN,
SHOCKLEY and BRATTAIN at Bell Labs.
• 1958 - JACK KILBY developed the first IC

• 1971 – Intel’s 4004 PMOS 4-bit processor @740K

• 1976 – Intel’s first Micro controller

• 1993- Pentium Processor

12.03.2012 11
 23 May 1908)
Born Madison, Wisconsin,
United States
January 30, 1991 (aged 82)
Died
Boston, Massachusetts
Nationality United States
Fields Physics

Bell Labs
John Bardeen Institutions University of Minnesota
University of Illinois at Urbana
-Champaign
University of Wisconsin-Madison
Alma mater
Princeton University
Doctoral
Eugene Wigner       
advisor
Doctoral John Schrieffer       
students Nick Holonyak
Transistor
Known for
BCS theory
Nobel Prize in Physics (1956)
Notable
Nobel Prize in Physics (1972)
awards
IEEE Medal of Honor (1971)
 February 10, 1902
Born
China-Amoy

October 13, 1987

Died

Nationality United States

Walter Houser Brattain

Fields Physicist, Inventor

Known for Transistor

Notable Nobel Prize in Physics

awards (1956)

12.03.2012 13
 13 February 1910)
Born
London, England
12 August 1989 (aged 79)
Died Stanford, California

Bell Labs
Institutions Shockley Semiconductor
Stanford
Caltech
Alma mater
William Shockley MIT
Doctoral
John C. Slater
advisor
Known for Co inventor of the transistor
Notable    
Nobel Prize in Physics
awards (1956)
Religious
None, atheist
stance

12.03.2012 14
 What is VLSI?
• Classification of ICs….. Based on no. of transistors

• In VLSI… Transistor count is in excess of 40 thousand

• A state of art of VLSI has more than 100 million transistors

• VLSI Chip…. Only CMOS transistors

• CAD tools are a must to design , verify and test the
VLSI chips
• SOC- System On Chip
• ASP-Application Specific Product using IP CORES

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 GORDON MOORE

Moore's Law: The number of

transistor is doubled in every 18
months—Gordon E. Moore

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12.03.2012 17
12.03.2012 18
12.03.2012 19
 Lead Microprocessors power continues to increase
100

P6
Pentium ® proc
Power (Watts)

10
486
8086 286
386
8085
1 8080
8008
4004

0.1
Year
1971 1974 1978 1985 1992 2000

Power delivery and dissipation will be prohibitive

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 Lead microprocessors frequency doubles every 2 years

10000

1000 2X every 2 years

Frequency (MHz)

P6
100
Pentium ® proc
486
10 8085 386
8086 286

1 8080
8008
4004
0.1
Year
1970 1980 1990 2000 2010

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Transistors on lead microprocessors double every 2 years

1000

100 2X growth in 1.96 years!

10
Transistors (M)

P6
Pentium® proc
1 486
386
0.1 286
8085 8086
0.01 8080
8008
4004
0.001
1970 1980 1990 2000 2010
Year

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VLSI Design Flow
VLSI DESIGN STYLES

Semi custom FPGA Based

Full Custom
Xilinx
Altera
Actel
Standard ……
Gate Array
cell Based ……
Based
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 System Idea

Sub Blocks Identification

Bottom – Up
(Full custom) Top Down
(Standard Cell)

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 Full Custom Flow
Sub Block
Schematic

LVS
Transistor level
Simulation
(Spice)
Post Layout
Simulation
Layout

Extraction

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 Standard Cell Flow

RTL Code

Placement &
Target Routing
Logic Synthesis (Std.Cells)
Library
& Target Library
Mapping

Post layout
Gate level Simulation
Net list

Digital
Simulation

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 Back End Flow
Full custom Standard cell

Placement & Routing

Prototyping
(Top level)

Top level Testing

Verification

Fabrication
Tape-out

12.03.2012 27
 CAD in VLSI

CONCEPT
E (Engg) CAD
T (Technology) CAD
VLSI
Ckt.
Design

VLSI Chip

CONCEPT- Defines the final Product Specification ( the

Product May be a Intel μP, Texas DSP or Motorola’s μC or it
could be an ASIC)

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 VLSI Processing
 Oxidation
 Diffusion/Ion Implantation
 Poly Deposition
 Etching
 Metallisation(vacuum/Sputtering)
 Testing
 SCRIBING And PACKAGING
 Testing…..Release To Market

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Agenda
Motivation
Introduction To VLSI Design
Sources Of Power Dissipation
Low Power Design Methodologies
Low Power Soc Designs
Low Power Multiplier Design
Design of Low Power MAC
Conclusion

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Power Equations in CMOS

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Techniques For Low Power
 Supply voltage

 Physical capacitance

 Switching Activity

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Dynamic
Vdd
power (Switching )

0 I charge
1

I discharge

Vss

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 Sources of Power Dissipation
2. Static Power = Leakage Power
= IL .VDD
IT

N+ N+ VDD
I Rev
P-Sub

Gate Tunneling current is a major

leakage power source in DSM ICs
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 Sources of Power Dissipation
3. Short Circuit Power
P short = ID Short . VDD
VDD
VDD

VDD/ ID Short
2

VGND VGND

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 Agenda
Motivation
Introduction To VLSI Design
Sources Of Power Dissipation
Low Power Design Methodologies
Low Power Soc Designs
Low Power Multiplier Design
Design of Low Power MAC
Conclusion

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Levels of Optimization

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Reduction of switching activity
• By proper choice of logic topology
• By circuit level optimization
representation of data can have significa
ct on switching activity at the system lev
se of Gray coding instead of binary codin
plications where data bits change sequen
as address bits

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Glitch Reduction
A D
B E
C
A
B
C
D
E
Glitch

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Glitch Reduction

• Delay balanced
Ex-or gates• No glitch
• Same function

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 Gated Clock Signals
A(N-1)
Reg MSB
B(N-1) Comparator
Clk
EX-OR
Reg (N-1)
Clk bit
Gated clock Comp-
arator
Inconventional approac
Reg
All bits are first latched
2 N-bit Regs, and
Subsequently applied to
comparator

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 Reduction of Switched Caps
System level Measures

C bus

rge bus Caps due to:

Large no.of drivers & receivers sharing the sam
The parasitic Cap.of the long bus
Global bus structure is partitioned into a
number of smaller
Dedicated local buses to handle data
transmission12.03.2012 42
 Circuit- Level Measures
• Cap is a function of the no. of
transistors in
a Logic circuit
• Use Pass-transistor (transmission
gates) logic
sing Xn gates one can construct 2:1 mux
nd a XOR gate with 6 Transistors against
2 and 14 transistors

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Leakage current/power
Dynamic Power is α V2dd
Static power is proportional to Vdd
So power reduces with the reduction of Vdd
With the scaling down of voltage and dimensions
Vth of the transistor is also scaled down
But leakage current increases exponentially in
sub-threshold region . So reduce leakage
current

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Variable Threshold CMOS
Leakage is reduced by turning OFF transistors not
in use
Use High Vt transistor for low I -leak and use Low
Vt transistor in critical path
So one should use transistors of different
threshold voltages

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Software Design For Low Power
Most efforts….focused on hardware design
It is because HW is the physical means by which
power is converted into useful computation
It would be unwise to ignore the influence of SW
on power dissipation
In systems based on digital processors or
controllers, it is SW that directs much of the
activity of the HW

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So , the manner in which SW uses the HW can
have a substantial impact on the power
dissipation of a system
Can draw an analogy from automobiles
The manner in which one drives his/her
automobile can have a significant effect on total
fuel consumption

12.03.2012 47
Agenda
Motivation
Introduction To VLSI Design
Sources Of Power Dissipation
Low Power Design Methodologies
Low Power Soc Designs
Low Power Multiplier Design
Design of Low Power MAC
Conclusion

12.03.2012 48
Introduction
 Power is a serious concern in
today's SoC design.
 Core based SoC design is common
to get time to market advantage.
 Cores are designed to be generic
and reusable with configurability.
 Need For Core customization.
 Core evaluation for Power

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SoC Composition

Analog Front
End Hard Macros
Digital core

Phy Spares SOC

PLL1

Serdes Memory
PLL2

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Agenda
Motivation
Introduction To VLSI Design
Sources Of Power Dissipation
Low Power Design Methodologies
Low Power Soc Designs
Low Power Multiplier Design
Design of Low Power MAC
Conclusion

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VLSI Signal Processing Building
Blocks
 Adder

 Multiplier

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Existing Low-power Techniques
 Partially Guarded Computation
(PGC).

 Dynamic-range Determination
(DRD).

 Glitching Power Minimization

(GPM).
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Partially Guarded Computation

inputs

clock
Detection logic Reg. 1 Reg. 2

latch

L
at
MSP LSP
c
h

Out puts

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Dynamic Range Determination
Dynamic range Dynamic range
determination determination

Large eff. Dynamic

range

Addition on the eff.

bit

Add to Match the

required word
length

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Glitching Power Minimization
 By replacing some existing gates with
functionally equivalent ones that can be “frozen”
by asserting a control signal.

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Main Functions in Multiplier
Partial products generation

Partial product compression

Partial product addition

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Array Multiplier

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Modified Booth Multiplier

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Spurious Power Suppression
Technique

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Proposed Multiplier-Demonstration

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Agenda
Motivation
Introduction To VLSI Design
Sources Of Power Dissipation
Low Power Design Methodologies
Low Power Soc Designs
Low Power Multiplier Design
Design of Low Power MAC
Conclusion

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Design of Low Power MAC

12.03.2012 63
Input Image And Its Pixel Values
1/9 1/9 1/9

1/9 1/9 1/9

Input image of the filter
1/9 1/9 1/9

Pixel value matrix of input image

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Output Image And Its Pixel Values

Output image of the filter

Pixel value matrix of output image

12.03.2012 65
Conclusions
State of art VLSI chip ( SOC) contains hundres of
million transistors
So it dissipates lot of power
To keep the packaging cost low….low power
technology
For portable devices low power ICs …a must
There are different low power design techniques

12.03.2012 66
 References
 Principles of CMOS VLSI Design---Neil weste and
K.Eshraghian
 ASICs -------M.J.Smith
 CMOS Design, layout and simulation R.Jacob
Baker
 Introduction to VLSI circuits & systems -----John
Uvemura
 Digital systems design using VHDL----Jr.Roth
 VHDL Primer----Jayaram Bhaskar
 Low-Power CMOS VLSI Circuit Design------Kaushik
Roy, Sharat Prasad

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THANK YOU

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