4 UNIT: MEMORY

●Organization, Functional Diagram, Memory

operations.
Classification of semiconductor memories, Read and
●

Write Memories, ROM.

●Programmable Logic Devices-PLAs, PALs and their
applications, Generic Array logic devices, Sequential
PLDs and their applications.
●Introduction to field programmable gate arrays
(FPGAs) and ASICS.
 MEMORY ORGANIZATION

• Memory Hierarchy

• Main Memory

• Auxiliary Memory

• Associative Memory

• Cache Memory

• Virtual Memory

• Memory Management Hardware

 Memory Hierarchy

MEMORY HIERARCHY

Memory Hierarchy is to obtain the highest possible

access speed while minimizing the total cost of the memory system
Auxiliary memory
Magnetic
tapes I/O Main
processor memory
Magnetic
disks

CPU Cache
memory

Register

Cache

Main Memory

Magnetic Disk

Magnetic Tape
 Main Memory

MAIN MEMORY
RAM and ROM Chips
Typical RAM chip

Chip select 1 CS1

Chip select 2 CS2
128 x 8
Read RD 8-bit data bus
RAM
Write WR
7-bit address AD 7

CS1 CS2 RD WR Memory function State of data bus

0 0 x x Inhibit High-impedence
0 1 x x Inhibit High-impedence
1 0 0 0 Inhibit High-impedence
1 0 0 1 Write Input data to RAM
1 0 1 x Read Output data from RAM
1 1 x x Inhibit High-impedence

Typical ROM chip

Chip select 1 CS1

Chip select 2 CS2
512 x 8 8-bit data bus
ROM

9-bit address AD 9
 Main Memory

MEMORY ADDRESS MAP

Address space assignment to each memory chip

Example: 512 bytes RAM and 512 bytes ROM

Hexa Address bus

Component address 10 9 8 7 6 5 4 3 2 1
RAM 1 0000 - 007F 0 0 0 x x x x x x x
RAM 2 0080 - 00FF 0 0 1 x x x x x x x
RAM 3 0100 - 017F 0 1 0 x x x x x x x
RAM 4 0180 - 01FF 0 1 1 x x x x x x x
ROM 0200 - 03FF 1 x x x x x x x x x

Memory Connection to CPU

- RAM and ROM chips are connected to a CPU
through the data and address buses

- The low-order lines in the address bus select

the byte within the chips and other lines in the
address bus select a particular chip through
its chip select inputs
 Main Memory

CONNECTION OF MEMORY TO CPU

Address bus CPU
16-11 10 9 8 7-1 RD WR Data bus

Decoder
3 2 1 0
CS1
CS2
RD 128 x 8
RAM 1
WR
AD7

Data
CS1
CS2
RD 128 x 8
RAM 2
WR
AD7

Data
CS1
CS2
RD 128 x 8
RAM 3
WR
AD7

CS1 Data
CS2
RD 128 x 8
RAM 4
WR
AD7
Data

CS1
CS2
1- 7 512 x 8
8 ROM
AD9
9
Data
Random Access Memory

Read Cycle

ECE 207 - Digital Electronics 7

Random Access Memory
Write Cycle

ECE 301 - Digital Electronics 8

 Concept

●Data storage essential for processing

●Binary storage
Write
●Switches

'0'
Read
'1'

● How do you implement this in Hardware?

 Requirements

●Easy reading
●Easy Writing

●High density

●Speed, more speed and still more speed

Semiconductor Memory Classification

Non-Volatile
Read-Write Memory Read-Write Read-Only Memory
Memory

Random Non-Random EPROM Mask-Programmed

Access Access 2
E PROM Programmable (PROM)

SRAM FIFO FLASH

DRAM LIFO
Shift Register
CAM

© Digital Integrated Circuits2nd Memories

Random Access Memory (RAM)
 Can be written to or read from.
Read/Write memory
Reading from RAM is non-destructive.

Access time to read from any memory

location is the same.
As compared to serial access memory.
Volatile

Information is lost when power is removed.

ECE 301 - Digital Electronics 12

Random Access Memory (RAM)

ECE 301 - Digital Electronics 13

Random Access Memory (RAM)
 Static Random Access Memory (SRAM)
Based on the Flip-Flop
Requires a large number of transistors
Fast
Dynamic Random Access Memory (DRAM)

Uses a single transistor to store charge

Requires very few transistors
Must be periodically refreshed
Slow(er)
ECE 301 - Digital Electronics 14
 RAM
●Random write and read operation for any cell
●Volatile data

●Most of computer memory

●DRAM

–Low Cost
–High Density
–Medium Speed
●SRAM

–High Speed
–Ease of use
 Basic Cells
SRAM
● DRAM
VDD

WL
WL
WL

DL
DL
DL
 Read Only Memory (ROM)
 Can only be read from.
 Memory is written (or “programmed”) once
 Reading from ROM is non-destructive.
Access time to read from any memory
location is the same.
Ascompared to serial access memory.
Non-Volatile

Information is retained even after power is

removed.
ECE 301 - Digital Electronics 17
Read Only Memory (ROM)

ECE 301 - Digital Electronics 18

 ROM

●Non-volatile Data
●Method of Data Writing

●Mask ROM

–Data written during chip fabrication

●PROM

–Fuse ROM: Non-rewritable

–EPROM: Erase data by UV rays
–EEPROM: Erase and write through electrical means
●Speed 2-3 times slower than RAM

●Upper limit on write operations

 ROM
EEPROM
● Fuse ROM
WL WL

Floating Gate

DL DL
 MOS NAND ROM
V DD
Pull-up devices

BL [0] BL [1] BL [2] BL [3]

WL [0]

WL [1]

WL [2]

WL [3]

All word lines high by default with exception of selected row

© Digital Integrated Circuits2nd Memories

 Programmable Logic Devices
PLD (generic)
●

–An IC where the logic function can be programmed into it after manufacture
–In some cases, it can be reprogrammed if a bug in the design is discovered

PLA (programmable logic array)

●

–Thefirst PLD on the market

–Two level AND/OR array structure with user programmable connections

PAL (programmable array logic)

●

–Appeared on the scene after PLA’s

–Lower cost
–The MSI of the programmable industry; sometimes simply called PLD

ROM (read-only memory)

●

–Originally not thought of as a programmable device at all – simply a memory for holding machine
specific information, such as the control store operation
CPLD (complex programmable logic device)
●

–A collection of PLD’s on a chip with programmable on-chip interconnections

FPGA (field programmable gate array)
●

–Another scheme developed same time as CPLD

–Large number of basic logic blocks (simple gates) with prog X/Y interconnection

R. W. Knepper, SC312
page O/V-16
 Programmable Logic Devices: CPLD vs FPGA
Complex Programmable Logic Device (CPLD): see (a) below
●

–Most of today’s CPLD’s are simply a collection of PLD’s on a chip with interconnected by programmable
interconnect (wiring)
Field Programmable Gate Array (FPGA): see (b) below
●

–FPGA’s are comprised of basic logic blocks interconnected by X and Y wiring channels

R. W. Knepper, SC312
page O/V-17
PROGRAMMABLE
LOGIC DEVICES
(PLD)
 PLD
•Problems by Using Basic Gates
•Many components on PCB:
–As no. of components rise, nodes interconnection
complexity grow exponentially
–Growth in interconnection will cause increase in
interference, PCB size, PCB design cost, and
manufacturing time
 PLD
•The purpose of a PLD device is to permit elaborate digital logic designs to be
implemented by the user in a single device.

•Can be erased electrically and reprogrammed with a new design, making them
very well suited for academic and prototyping

•Types of Programmable Logic Devices

•SPLDs (Simple Programmable Logic Devices)
–ROM (Read-Only Memory)
–PLA (Programmable Logic Array)
–PAL (Programmable Array Logic)
–GAL (Generic Array Logic)
•CPLD (Complex Programmable Logic Device)
•FPGA (Field-Programmable Gate Array)
 PLD
•The first three varieties are quite similar to each other:
–They all have an input connection matrix, which connects the inputs of
the device to an array of AND-gates.
–They all have an output connection matrix, which connect the outputs
of the AND-gates to the inputs of OR-gates which drive the outputs of
the device.

•The gate array is significantly different and will be described

later.
 PLD
•The differences between the first three categories are
these:
–1. In a ROM, the input connection matrix is hardwired. The user
can modify the output connection matrix.
–In a PAL/GAL the output connection matrix is hardwired. The user
can modify the input connection matrix.
–In a PLA the user can modify both the input connection matrix and
the output connection matrix.
General structure of PLDs.
 Buffer/inverter

(a) Symbol. (b) Logic equivalent.

 Programming by blowing fuses.

(a) Before programming. (b) After programming.

OR - PLD Notation
AND - PLD Notation
PROM Notation
 Using a PROM for logic design

(a) Truth table. (b) PROM realization.

Advantages of PLA

 Efficient in terms of area needed for implementation on an IC chip

 Often included as part of larger chips such as microprocessors

 Programmable AND and OR gates

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PAL - Programmable Array Logic

PLA have higher programmability than PAL, however they have lower
speed than PAL

Solution  PAL for higher speed.

 Programmable AND, Fixed OR

 PAL - Simpler to manufacture, cheaper than PLA and have better

performance

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A simple four-input, three-output PAL device.
An example of using a PAL device to realize two
Boolean functions. (a) Karnaugh maps. (b) Realization.
 Flip-flops store the value produced by the OR gate output at a particular
point and can hold it indefinitely.

 Flip-flop output is controlled by the clock signal. On 0-1 transition of

clock, flip-flop stores the value at its D input and latches the value at Q
output.

 2-to-1 multiplexer selects an output from the OR gate output or the flip-flop
output. Tri-state buffers are placed between multiplexer and the PAL output.

 Multiplexer’s output is fed back to the AND plane in PAL, which allows the
multiplexer signal to be used internally in the PAL. This facilitates the
implementation of circuits that have multiple stages (levels or logic gates).

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 FPGA AND CPLD
1.FPGA - Field-Programmable Gate Array.
2.CPLD - Complex Programmable Logic Device
3.FPGA and CPLD is an advance PLD.
4.Support thousands of gate where as PLD only
support hundreds of gates.
 What is an FPGA?
•Before the advent of programmable logic, custom logic circuits were built at the board
level using standard components, or at the gate level in expensive application-specific
(custom) integrated circuits.

•FPGA is an integrated circuit that contains many (64 to over 10,000) identical logic
cells that can be viewed as standard components. Each logic cell can independently
take on any one of a limited set of personalities.

•Individual cells are interconnected by a matrix of wires and programmable

switches. A user's design is implemented by specifying the simple logic function for
each cell and selectively closing the switches in the interconnect matrix.

•Array of logic cells and interconnect form a fabric of basic building blocks for logic
circuits. Complex designs are created by combining these basic blocks to create the
desired circuit
FPGA architecture
 What does a logic cell do?
•The logic cell architecture varies between different device families.

•Each logic cell combines a few binary inputs (typically between 3 and 10) to one or
two outputs according to a Boolean logic function specified in the user program .

•In most families, the user also has the option of registering the combinatorial output of
the cell, so that clocked logic can be easily implemented.

•Cell's combinatorial logic may be physically implemented as a small look-up table

memory (LUT) or as a set of multiplexers and gates.

•LUT devices tend to be a bit more flexible and provide more inputs per cell than
multiplexer cells at the expense of propagation delay.
 what does 'Field Programmable' mean?
•Field Programmable means that the FPGA's function is defined by a user's program
rather than by the manufacturer of the device.

•A typical integrated circuit performs a particular function defined at the time of

manufacture. In contrast, the FPGA's function is defined by a program written by
someone other than the device manufacturer.

•Depending on the particular device, the program is either 'burned' in permanently or

semi-permanently as part of a board assembly process, or is loaded from an external
memory each time the device is powered up.

•This user programmability gives the user access to complex integrated designs
without the high engineering costs associated with application specific integrated
circuits.
 How are FPGA programs created?
•Individually defining the many switch connections and cell logic functions would be a
daunting task.

•This task is handled by special software. The software translates a user's schematic
diagrams or textual hardware description language code then places and routes the
translated design.

•Most of the software packages have hooks to allow the user to influence
implementation, placement and routing to obtain better performance and utilization of
the device.

•Libraries of more complex function macros (eg. adders) further simplify the design
process by providing common circuits that are already optimized for speed or area.
 FPGA
FPGA applications:-
i.DSP
ii.Software-defined radio
iii.Aerospace
iv.Defense system
v.ASIC Prototyping
vi.Medical Imaging
vii.Computer vision
viii.Speech Recognition
ix.Cryptography
x.Bioinformatic
xi.And others.
 CPLD
1.Complexity of CPLD is between FPGA and PLD.
2.CPLD featured in common PLD:-
i.Non-volatile configuration memory – does not need an external configuration PROM.
ii.Routing constraints. Not for large and deeply layered logic.

3.CPLD featured in common FPGA:-

i.Large number of gates available.
ii.Can include complicated feedback path.
4.CPLD application:-
i.Address coding
ii.High performance control logic
iii.Complex finite state machines
 CPLD

5.CPLD architecture:-

LAB – Logic Array Block / uses PALs

PIA – Programmable Interconnect Array
The distinction between the two is blurred
Although PLDs started as small devices, today’s PLDs are anything but simple.
FPGAs fill the gap between PLDs and complex ASICs
In both cases, you can program the devices yourself, using design entry and simulation.
All FPGAs have regular array of basic cells that are configured by the programmer using special
software that program the chips by programming the interconnection.
Each vendor has tool supplier that provides custom tools for their products.
The programming methodology is usually non permanent, allowing re-programmability

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