Sei sulla pagina 1di 46

Computer Architecture I: Digital Design

Dr. Robert D. Kent

CPU Registers

Register Transfer and Microoperations


Review
• We have introduced registers previously.

• Registers are constructed using flip-flops and


combinational circuits that enable one to:

– Refresh volatile data


– Load (Store) data
– Clear storages (change all bits to 0)
– Increment (and decrement) storages binarily
– Complement storages
– Select individual storage bits
Considering the next problem in design
• When designing complex computer systems it is important to
understand that we start from very small components for
which the operational characteristics are extremely well
defined.

• We then applied Bottom-Up Hierarchical design to identify


commonly used networks (ie. circuits) of smaller
components, from SSI to MSI. At this stage the descriptive
language (and symbols) changes.
– SSI: + as OR transforms to MSI: + as ADD

• Now as we consider MSI to LSI, and also MSI-to-MSI


networks, such as the CPU, our language must again
change to fit the nature of design.
Goals
• The Mano model of the CPU Registers
– Registers
– Bus network

• Register and Memory Transfer


– A language for describing hardware function
– A language for denoting implementation
– A language that bridges LSI/MSI

• Microoperations: Application examples


– Arithmetic
– Logic
– Shift
The Mano model of the CPU Registers
• CPU registers used in the textbook (Mano):

– PC :: Program counter
– IR :: Instruction register

– AR :: Address register
– DR :: Data register
(also called MBR – Memory Buffer Reg.)

– AC :: Accumulator
– INR :: Input buffer register
– OUTR :: Output buffer register
– SCR :: Sequence counter register
The Mano model of the CPU Registers
• CPU registers are organized on an internal bus network
– Accessible using a multiplexer
– Registers are selected according to selection inputs

0 PC Typically, the
1x8 8x1 number of registers
1 AR is chosen as a
MUX MUX
2 DR power of 2.
Data 3 IR Data This simplifies the
IN OUT choice of MUX and
4 AC the bus
5 INR architecture.

S S S
6 OUTR S S S Demultiplexers are
2 1 0 7 SCR 2 1 0 used to input data
to registers.

Register Register
Address Address
Reminder!
• CPU register operations should be among the
fastest of hardware operations

– All instructions are executed in CPU


– Few registers implies more complex circuits may be
employed to control data processing and workflow

– We need a language that allows us to describe what we


want to happen (operationally) in a circuit, while achieving
an actual working hardware system to accomplish our
requirements
• We must also understand the complexities or behaviours of
the circuits, such as performance based on numbers of logic
stages, degrees of parallel versus serial capacity, response
and other factors
Register Transfer
• First, review what we have learned so far about registers
– We combined the basic building blocks of bit storage units (ie.
flip-flops) to form storage units of multiple bits called
registers
– We combined registers with more complicated circuitry to
perform various operations
• Some serial operations
• Some parallel operations
– We combined several operations together into even more
complicated circuits
• The choice of operation is determined by Selector inputs using
either Multi-Input Control, or Multiplexer Selection.
Register – Parallel Load
• Register flip-flops should refresh or load simultaneously.

Load
Single Operation

D Q P0
I0 C

D Q P1
I1 C

Clk
Register – Count/Load/Clear
• Combine counting (INC), loading (L) and synchronous
clearing (C). Can also add Complementation (J=K=1).
C
L
Inc Multi-Input Selection:
J Q A0
I0 C
Multiple Operations
K

J Q A1
I1 C
Carry
K
Out

(See Fig. 2-11 in Mano)


Clk
Register – Shift/Load/Refresh

• Bi-directional shifting can be combined with parallel load and


refresh operations. This requires use of multiplexers.
Function Table

Mode
Control
S1 S0 Register Operation

0 0 Refresh – no change

0 1 Shift right

1 0 Shift left

1 1 Parallel load
Register – Shift/Load/Refresh
• Bi-directional shifting can be combined with parallel load and
refresh operations.

S0 S0
S1
Multiplexer
S1
Selection:
D Q A0

0 4x1 C
Serial in
Multiple
1 MUX
Operations
2
I0 3

S0
D Q A1
S1
0 4x1 C
1 MUX
Serial in
2
I1 3
(See Fig. 2-9 in Mano)
Clk
Registers: Multi-Operation Control
• Selection of specific operations (or even groups of
operations) can be accomplished in several ways.

– Single selection
• Dedicated circuits

– Multi-selection
• Multiplexed selection
• Multi-input selection
• Hybrid selection, combining both multiplexers and multi-inputs

• Unfortunately we do not have time to discuss the fullest


implications of this important topic.
– Interested students should read advanced chapters of Mano
(Chapter 6 and higher).
Register Transfer
• The internal hardware organization of a digital computer is
best defined by specifying:

– The set of registers it contains and their function


– The sequence of microoperations performed on the binary
data stored in the registers
– The control that initiates the sequence of microoperations
Register Transfer
• Notations and conventions:

• Copy (ie. transfer) all data from one register (R1) to another (R2).
– May be parallel or serial, but we do not need to ask

R2 R1

R2 = R1 :: Use ‘=‘ for print convenience


Register Transfer
• Notations and conventions:

• If we intend to copy only a portion of data it is important to specify


precisely where the data is located within the storage.
R : High Low
R1 76543210

(a) Complete Register R1 (b) Individual bits within R, such


as R(0-7), R(15), R(L)

15 0 15 87 0
R2 PC (H) PC (L)

(c) Numbering of bits in R2 (d) PC register divided into a


High and a Low part
Register Transfer

• Notations and conventions:

• Conditional transfer

– If ( P = = 1) then ( R2 R1 )

• This can be rewritten in the compact form:

– P: R2 R1

• Finally, we can combine several operations in parallel:

– T: R2 R1 , R4 R3

Parallel operations in hardware must be


carefully checked for consistency to ensure
they are sensible (achievable) and not just
nonsense.
Memory
• RAM storages are typically constructed as a single unit
called a byte.
• Although the standard storage unit for data is 8-bits
(flip-flops), additional bits are used for a variety of
purposes
– especially error checking (Hamming Codes)
• Each byte is located at a fixed address
– Starts at address 0 and increases contiguously up to a
maximum address, usually a power of 2
– Review lecture on multiplexers as address selectors
enabling data transfer from selected bytes
• The byte is called the smallest unit of addressable
memory.
Memory Transfer
• We reserve the letter M to denote volatile memory (ie.
RAM)
• Data in memory needs to be referenced by its location, or
address
Read operation : DR = M[AR]

– M[address] :: refers to the data stored at “address”


Write operation : M[AR] = DR

– M[04C8] :: refers to the data stored at address 04C8

– M[AR] :: refers to the data stored at the address which


is itself stored in the register AR (address register)
Microoperations
Micro-operations are considered fundamental, or
primitive (usually atomic) operations carried out in the
CPU or elsewhere.

1. Register transfer microoperations transfer binary


data from one register to another register.
2. Arithmetic microoperations perform arithmetic
operations on numeric data stored in registers.
3. Logic microoperations perform bit manipulation
operations on non-numeric data stored in
registers.
4. Shift microoperations perform shift operations
on data stored in registers.
Arithmetic Microoperations

• Arithmetic microoperations perform arithmetic operations on


numeric data stored in registers.

Arithmetic Microoperations
Symbolic Descriptive
R3 = R1 + R2 Contents of R1 plus R2 transferred to R3
R3 = R1 – R2 Contents of R1 minus R2 transferred to R3
R1 = ~R1 1’s complement the contents of R1
R2 = ~R2 + 1 2’s complement the contents of R2 (negate)
R3 = R1 + ~R2 + 1 R1 plus 2’s complement of R2 (subtraction)
R1 = R1 + 1 Increment the contents of R1 by one
R2 = R2 – 1 Decrement the contents of R2 by one
Arithmetic Microoperations

• Arithmetic microoperations perform arithmetic operations on


numeric data stored in registers.

Arithmetic Microoperations
Symbolic Descriptive
R3 = R1 + R2 Contents of R1 plus R2 transferred to R3
R3 = R1 – R2 Contents of R1 minus R2 transferred to R3
R1 = ~R1 1’s complement the contents of R1
R2 = ~R2 + 1 2’s complement the contents of R2 (negate)
R3 = R1 + ~R2 + 1 R1 plus 2’s complement of R2 (subtraction)
R1 = R1 + 1 Increment the contents of R1 by one
R2 = R2 – 1 Decrement the contents of R2 by one
Arithmetic Microoperations

• Arithmetic microoperations perform arithmetic operations on


numeric data stored in registers.

Arithmetic Microoperations
Symbolic Descriptive
R3 = R1 + R2 Contents of R1 plus R2 transferred to R3
R3 = R1 – R2 Contents of R1 minus R2 transferred to R3
R1 = ~R1 1’s complement the contents of R1
R2 = ~R2 + 1 2’s complement the contents of R2 (negate)
R3 = R1 + ~R2 + 1 R1 plus 2’s complement of R2 (subtraction)
R1 = R1 + 1 Increment the contents of R1 by one
R2 = R2 – 1 Decrement the contents of R2 by one
Arithmetic Microoperations

• Arithmetic microoperations perform arithmetic operations on


numeric data stored in registers.

Arithmetic Microoperations
Symbolic Descriptive
R3 = R1 + R2 Contents of R1 plus R2 transferred to R3
R3 = R1 – R2 Contents of R1 minus R2 transferred to R3
R1 = ~R1 1’s complement the contents of R1
R2 = ~R2 + 1 2’s complement the contents of R2 (negate)
R3 = R1 + ~R2 + 1 R1 plus 2’s complement of R2 (subtraction)
R1 = R1 + 1 Increment the contents of R1 by one
R2 = R2 – 1 Decrement the contents of R2 by one
Arithmetic Microoperations

• Arithmetic microoperations perform arithmetic operations on


numeric data stored in registers.

Arithmetic Microoperations
Symbolic Descriptive
R3 = R1 + R2 Contents of R1 plus R2 transferred to R3
R3 = R1 – R2 Contents of R1 minus R2 transferred to R3
R1 = ~R1 1’s complement the contents of R1
R2 = ~R2 + 1 2’s complement the contents of R2 (negate)
R3 = R1 + ~R2 + 1 R1 plus 2’s complement of R2 (subtraction)
R1 = R1 + 1 Increment the contents of R1 by one
R2 = R2 – 1 Decrement the contents of R2 by one
Arithmetic Microoperations

• Multiple operations can be multiplexed together

– Adder-Subtractor
– Shift Left/Right
• Logical
• Arithmetic
– Increment/Decrement
– Load
– And so on ….
Arithmetic Microoperations
• Arithmetic microoperations perform arithmetic operations on
numeric data stored in registers.
Arithmetic Circuit Function Selection Table
Select Input Output
S1 S2 Cin Y D = A + Y + Cin Microoperation
0 0 0 B D=A+B Add
0 0 1 B D=A+B+1 Add with carry
0 1 0 ~B D = A + ~B Subtract with borrow
0 1 1 ~B D = A + ~B + 1 Subtract
1 0 0 0 D=A Transfer A
1 0 1 0 D=A+1 Increment A
1 1 0 1 D=A-1 Decrement A
1 1 1 1 D=A Transfer A
Arithmetic Microoperations
• Arithmetic microoperations perform arithmetic operations on
numeric data stored in registers.
Arithmetic Circuit Function Selection Table
Select Input Output
S1 S2 Cin Y D = A + Y + Cin Microoperation
0 0 0 B D=A+B Add
0 0 1 B D=A+B+1 Add with carry
0 1 0 ~B D = A + ~B Subtract with borrow
0 1 1 ~B D = A + ~B + 1 Subtract
1 0 0 0 D=A Transfer A
1 0 1 0 D=A+1 Increment A
1 1 0 1 D=A-1 Decrement A
1 1 1 1 D=A Transfer A
Arithmetic Microoperations
Note that S1 and S2 are
• Arithmetic microoperations perform arithmetic
multiplexer selector inputs, operations on
numeric data stored in registers.
whereas Cin is a separated
input.
Arithmetic Circuit Function Selection Table
Select Input Output
S1 S2 Cin Y D = A + Y + Cin Microoperation
0 0 0 B D=A+B Add
0 0 1 B D=A+B+1 Add with carry
0 1 0 ~B D = A + ~B Subtract with borrow
0 1 1 ~B D = A + ~B + 1 Subtract
1 0 0 0 D=A Transfer A
1 0 1 0 D=A+1 Increment A
1 1 0 1 D=A-1 Decrement A
1 1 1 1 D=A Transfer A
Logic Microoperations
• Logic microoperations perform bit manipulation operations on
non-numeric data stored in registers.
Logic Microoperations 4 0 1

0 1 1

• 1
Consider all possible bit operations involving 2 inputs 1 1

0 0 1 1 0 1 1 0 1 1 0 1 1 0 1

0 0 0 0 1 0 1 0 0

1 0 0 1 1 1 1 1 1

2 0 1 2 0 1 2 0 1 2 0 1 2 0 1

0 1 1 0 1 0 1 0 1 0 1

1 1 1 1 1 1 1 1 1

2 0 1 3 0 1 3 0 1 3 0 1 3 0 1

0 0 1 1 0 1 1 0 1 0 1

1 1 1 1 1 1 1 1 1 1 1 1 1
Logic Microoperations
• By labeling each possible operation we derive the following
table.
Sixteen Fundamental Logic Microoperations
MicroOp Name MicroOp Name
0 F=0 Clear 8 F = A’B’ NOR (A+B)’
1 F = AB AND 9 F = AB+A’B’ eXclusive NOR
2 F = AB’ Selective clear A 10 F = B’ Complement B
3 F=A Transfer A 11 F = A+B’ Selective set A
4 F = A’B Selective clear B 12 F = A’ Complement A
5 F=B Transfer B 13 F = A’+B Selective set B
6 F = AB’+A’B eXclusive OR 14 F = A’+B’ NAND (AB)’
7 F = A+B OR 15 F = 1 Set
Logic Microoperations
• Refer to Mano

– Multiplexed Logic Circuit (Figure 4.10)

– Applications discussion, pages 11-113


Shift Microoperations
• Shift microoperations perform shift operations on data stored in
registers.
Shift Microoperations
Symbolic Descriptive
R = shl R Shift-left logical register R
R = shr R Shift-right logical register R
R = cil R Circular shift-left register R
R = cir R Circular shift-right register R
R = ashl R Shift-left arithmetic register R
R = ashr R Shift-right arithmetic register R
Shift Microoperations
• Shift microoperations perform shift operations on data stored in
registers.
Shift Microoperations
Symbolic Descriptive
R = shl R Shift-left logical register R
R = shr R Shift-right logical register R
R = cil R Circular shift-left register R
Shift left
R = cirorder
High R Circular shift-right register R
Low Order
RBit
= ashl
Loss R Shift-left arithmetic register R
Input 0
R = ashr R Shift-right arithmetic register R

Shift right
High order
Low Order
Input 0
Bit Loss
Shift Microoperations
• Shift microoperations perform shift operations on data stored in
registers.
Circular
Shift shift left
Microoperations
HighSymbolic
order Descriptive Low order
to Low
R order
= shl R Shift-left logical register R from High order
R = shr R Shift-right logical register R
R = cil R Circular shift-left register R
R = cir R Circular shift-right register R
R = ashl R Shift-left arithmetic register R
Circular shift right
R = ashr R Shift-right arithmetic register R
High order Low order
From Low order to High order
Shift Microoperations
• Shift microoperations perform shift operations on data stored in
registers.
Shift Microoperations
Symbolic Descriptive
R = shl R Shift-left
Arithmeticlogical register
shift left R
High
R order
= shr R Shift-right logical register R
Low Order
RBit Loss
= cil R Circular shift-left register R
Input 0
R = cir R Circular shift-right register R
R = ashl R Shift-left arithmetic register R
R = ashr R Shift-right arithmetic register R

Arithmetic shift right


High order Low order
Input High order Bit Loss
Shift Microoperations
• Shift microoperations perform shift operations on data stored in
registers.
Shift Microoperations
Symbolic Descriptive
R = shl R Shift-left logical register R
R = shr R Shift-right logical register R
R = cil R Circular shift-left register R
R = cir R Circular shift-right register R
R = ashl R Shift-left arithmetic register R
R = ashr R Shift-right arithmetic register R
Shift Microoperations
Assume registers have L bits, each represented by a D flip-flop.

F(i)
0 Load
~F(i)
1 Complement
i=0?0:F(i-1)
2 shl
i=L-1?0:F(i+1)
3 shr 8x1
F( (L+i-1)%L ) D Q F(i)
4 cil MUX
F( (L+i+1)%L ) FF(i)
5 cir
i=0?0:F(i-1)
6 ashl
i=L-1?F(L):F(i+1)
7 ashr
REGISTER
E Enable
S2 S1 S0

SELECTION CONTROL
Shift Microoperations
Assume registers have L bits, each represented by a D flip-flop.

F(i)
0 Load
~F(i)
1 Complement
Example: L = 5
i=0?0:F(i-1)
2 shl
i=L-1?0:F(i+1)
3 shr 3x8
SHR :: F(4) = 0
F( (L+i-1)%L ) D Q F(i)
4 cil DEC F(3) = F(4)
F( (L+i+1)%L ) FF(i)
5 cir CIR :: F(4) = F( (5+4+1)%5 ) = F(0)
i=0?0:F(i-1)
6 ashl F(3) = F(4)
i=L-1?F(L):F(i+1)
7 ashr ASHR :: F(4) = F(4)
F(3) = F(4)
E Enable
S2 S1 S0
Arithmetic Logic Shift Unit
• Mano discusses a multi-stage circuit
– Arithmetic stage
– Logic stage
– Multiplexed selection of operation

• Read
– Accompanying text
More Advanced Microoperations
• The following topics are discussed later in Mano (3d
Edition Chapters 6-10) and will be studied in the course
60-460 (Advanced Architecture).
– Integer Multiplication & Division
– Floating Point Architectures
• FP Register design
• FP Microoperations
– Input/Output Architectures
• The discussion in the lecture is oral and conceptual.
There are no points discussed that are important for
examinations – this is optional material that will not be
tested.
Three-State Buffers
• An important device called a 3-state bus buffer has been
developed.
– Basically a capacitor with an impedance trigger
– Capacitors can hold a charge (equivalently, a voltage level)
for a long time until an event triggers the release of the
charge (equivalently, allows a voltage level to pass onto a
connecting wire). Impedance refers to a property of electrical
circuits, where current does not flow
between connected wires or gates unless
Input Output the impedances match in the connected
sub-systems.
A Y
Thus, if C=0, no signal flows from A to Y.
C Y is therefore not defined.
Control However, if C=1, impedances are matched
and signal flows from A to Y.
The value at Y is then A.
Three-State Buffers
• 3-state bus buffers are
often used at the outputs
of storage flip-flops.
Bus line for bit K
– Essentially, the buffer unit R0
“holds” the value stored in
the FF. R1
– Holding is useful for
synchronizing enabling of R2
parallel circuits
R3
• The buffer unit can be
used along with a Decoder
unit as a replacement for Select { S0
S1
2x4
0
1
DEC
an address multiplexer. 2
(K)
– This is an alternative Enable E 3
approach.
Three-State Buffers
• 3-state bus buffers are
often used at the outputs
of storage flip-flops.
Bus: R2(K)
– Essentially, the buffer unit R0
“holds” the value stored in
the FF. R1
– Holding is useful for
synchronizing enabling of R2
parallel circuits
R3
• The buffer unit can be
0
used along with a Decoder
unit as a replacement for Select { S0
S1
2x4
0
1
1 DEC
an address multiplexer. 2
(K)
– This is an alternative Enable E 3
approach. 1
Summary
• We introduced Mano’s basic CPU architecture
– Registers
– Bus
• We discussed Register and Memory Transfer and
introduced a language suitable for description and
design
• We presented several example applications of
RTL/MTL for Microoperations
– Arithmetic
– Logic
– Shift
• We discussed briefly more advanced applications

Potrebbero piacerti anche