BIOS and DOS Interrupts

Basic Input /Outpu System

Disk Operating System
 Computer Interrupt

Interrupt request: a signal that immediate attention is

needed

Interrupt processing: what CPU does in response to request

Interrupt service: what is done in software as a result

 Computer Interrupt

2 General Types of Interrupts:

External - generated outside CPU by other hardware

Internal - generated within CPU as a result of instruction or operation
- x86 internals: int, into, divide error, and single step
- “trap” generally means any processor generated interrupt;
in x86, usually means the single step interrupt

•x86 Terminology for Interrupts:

1) Hardware Interrupt – External, uses INTR and NMI control bus lines
2) Software Interrupt – Internal, from int or into
3) Processor Interrupt – traps, exceptions
 8086/8088 Pinout Diagrams
GND 1 40 VCC GND 1 40 VCC
AD14 2 39 AD15 A14 2 39 A15
AD13 3 38 A16/S3 A13 3 38 A16/S3
AD12 4 37 A17/S4 A12 4 37 A17/S4
AD11 5 36 A18/S5 A11 5 36 A18/S5
AD10 6 35 A19/S6 A10 6 35 A19/S6
AD9 7 34 BHE/S7 A9 7 34 SS0
AD8 8 33 MN/MX A8 8 33 MN/MX
AD7 9 8086 32 RD AD7 9 8088 32 RD
AD6 10 31 HOLD AD6 10 31 HOLD
AD5 11 30 HLDA AD5 11 30 HLDA
AD4 12 29 WR AD4 12 29 WR
AD3 13 28 M/IO AD3 13 28 IO/M
AD2 14 27 DT/R AD2 14 27 DT/R
AD1 15 26 DEN AD1 15 26 DEN
AD0 16 25 ALE AD0 16 25 ALE
NMI 17 24 INTA NMI 17 24 INTA
INTR 18 23 TEST INTR 18 23 TEST
CLK 19 22 READY CLK 19 22 READY
GND 20 21 RESET GND 20 21 RESET

8086 8088
Pin Mode Pin Mode
Minimum Maximum Minimum Maximum
31 HOLD RQ/GT0 31 HOLD RQ/GT0
30 HLDA RQ/GT1 30 HLDA RQ/GT1
29 WR LOCK 29 WR LOCK
28 M/IO S2 28 IO/M S2
27 DT/R S1 27 DT/R S1
26 DEN S0 26 DEN S0
25 ALE QS0 25 ALE QS0
24 INTA QS1 24 INTA QS1
34 SS0 High State
 8086 External Interrupt Connections
NMI - Non-Maskable Interrupt INTR - Interrupt Request

Programmable
NMI Requesting Interrupt Controller
Device (part of chipset)

NMI
8086 CPU
Intel
INTR
Interrupt Logic 8259A
PIC
Divide Single
int into
Error Step

Software Traps
 Interrupt Vector Table – IVT (in memory)

• x86 has 256 interrupts, specified by Type Number or Vector

• 1 byte of data must accompany each interrupt; specifies Type
• Vector is a pointer (address) into Interrupt Vector Table, IVT
– IVT is stored in memory from 0000:0000 to 0000:03ffh

• IVT contains 256 far pointer values (addresses)

– Far pointer is CS:IP values

• Each far pointer is address of Interrupt Service Routine, ISR

– Also referred to as Interrupt Handler

When interrupt is requested, which IVT entry? Type!

 IVT Format
0000:0000
0000:0001
Offset
0000:0002
Interrupt 0 IP LSB

0000:0003
Segment IP MSB

0000:0004 CS LSB

0000:0005
Offset CS MSB
Interrupt 1
0000:0006
0000:0007
Segment

Given a Vector, where is the

ISR address stored in memory ?

Offset  Type  4
0000:03fc
0000:03fd
Offset Example: int 36h
0000:03fe
Interrupt 255
0000:03ff
Segment Offset = (544) = 216
= 00d8h
What Happens During an Interrupt ?
Complete push
Current Flags
Instruction

Internal
YES Set
TEMP=TF
TF=TEMP
Interrupt

NO

YES IF=0 pop

NMI TF=0 IP and CS
NO

YES 1
push
INTR IF popf
CS and IP
0
NO

1 acknowledge call Resume

TF Interrupted
interrupt ISR Procedure
0

Fetch Read Type

YES
Next Code # NMI
Instruction
NO
 Similarity to Subroutine Procedure
call  int
ret  iret
• call pushes CS, IP and loads CS:IP with address of subroutine

• int does what call does and more

• ret pops IP, CS

• iret pops FLAGS, IP, and CS

This is why ALL programs MUST have a stack segment, so that interrupts can be
handled
 halt Instruction
• This instruction causes processor to enter a HALT state
• HALT state is one where no further instructions are fetched nor executed until
one of the following events occurs:

1) System is reset - rising edge on RESET pin

2) External interrupt occurs

CPU Asset Content

FLAGS Register 0000h
IP 0000h
CS ffffh
DS 0000h
SS 0000h
ES 0000h
Instruction Queue Empty
 Interrupt Vector Assignments
Type Function
0 Divide Error
1 Single Step (DEBUG)
2 Nonmaskable Interrupt Pin
3 Breakpoint
4 Arithmetic Overflow
5 Print Screen Key
6 Invalid Opcode
7 Coprocessor Not Present
8 Time Signal
9 Keyboard Service
A-F Originally Bus Ops (IBM PC)
10 Video Service Request
11 Equipment Check
12 Memory Size
13 Disk Service Request
14 Serial Port Service Request
15 Miscellaneous
16 Keyboard Service Request
Comment
Processor - zero or overflow
Processor - TF=1
Processor - NMI Signal
Processor - Similar to Sing Step
Processor - into
BIOS - Key Depressed
Processor - Invalid Opcode
Processor - no FPU
BIOS - From RT Chip (AT - IRQ0)
BIOS - Gen Service (AT - IRQ1)
BIOS - (AT - IRQ2-7)
BIOS - Accesses Video Driver
BIOS - Diagnostic
BIOS - DOS Memory
BIOS - Accesses Disk Driver
BIOS - Accesses Serial Port Drvr
BIOS - Cassette, etc.
BIOS - Accesses KB Driver
Interrupt Vector Assignments (cont.)
Type Function Comment
17 Parallel Port LPT Service BIOS - Printer Driver
18 ROM BASIC BIOS - BASIC Interpreter in ROM
19 Reboot BIOS - Bootstrap
1A Clock Service BIOS - Time of Day from BIOS
1B Control-Break Handler BIOS - Keyboard Break
1C User Timer Service BIOS - Timer Tick
1D Pointer to Video Parm Table BIOS - Video Initialization
1E Pointer to Disk Parm Table BIOS - Disk Subsystem Init.
1F Pointer to Graphics Fonts BIOS - CGA Graphics Fonts
20 Program Terminate DOS - Clear Memory, etc.
21 Function Call DOS - Transfer Control
22 Terminate Address DOS - program Terminate handler
23 Control-C Handler DOS - For OS Use
24 Fatal Error Handler DOS - Critical Error
25 Absolute Disk Read DOS - Disk Read
26 Absolute Disk Write DOS - Disk Write
27 Terminate DOS - TSR Usage
28 Idle Signal DOS - Idle
2F Print Spool DOS - Cassette, etc.
70-77 Hardware Interrupts in AT Bios DOS - (AT - IRQs 8-15)
 AT – IRQ Definitions
IBM-AT (Advanced Technology) - Intel 80286
Name Interrupt Vector Priority Description
NMI 02 1 Memory Parity Error
IRQ0 08 2 Timer (Intel 8253 Chip 55 ms intervals)
IRQ1 09 3 Keyboard
IRQ2 0A 4 8259 PIC Slave or EGA/VGA Vert. Retrace
IRQ3 0B 13 Serial Port (COM2 or COM4)
IRQ4 0C 14 Serial Port (COM1 or COM3)
IRQ5 0D 15 Fixed Disk or LPT2 Request
IRQ6 0E 16 Floppy Disk Driver
IRQ7 0F 17 LPT1 Request
IRQ8 70 5 CMOS Real-Time Clock (RT Chip)
IRQ9 71 6 Re-directed to IRQ2
IRQ10 72 7 RESERVED
IRQ11 73 8 RESERVED
IRQ12 74 9 Mouse or other
IRQ13 75 10 Math Coprocessor (NPX)
IRQ14 76 11 Hard Disk
IRQ15 77 12 RESERVED
 Interrupt Service Routines
• ALL Interrupts
• Interrupts for Inpu
• Interrupts for Output
 Interrupts for Inpu
• INT 16h / AH = 00h - get keystroke from keyboard (no
echo)
• INT 16h / AH = 01h - check for keystroke in the
keyboard buffer
• INT 21h / AH=1 - read character from standard input,
with echo
• INT 21h / AH=6 - direct console input or output
• INT 21h / AH=7 - character input without echo to AL
• INT 21h / AH=0Ah - input of a string
• INT 21h / AH=0Bh - get input status
 Interrupts for Output
• INT 21h / AH=2 - write character to standard
output
• INT 21h / AH=9 - output of a string
 HW#1
• Develop an assembly program that receives a
decimal number (up to max 100 digits) from user
and displays its hexadecimal equivallent.

• Due Date: Sunday Esfand 23rd

• Mail to: Mr Kazari and me (vahdat@sharif.edu or
vosoughivahdat@yahoo.com)
• Subject: HW1 UPI2010 IDxxxxxxxx