INTRODUCTION TO

EMBEDDED SYSTEMS
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BUS STRUCTURE

Created by Mr. THOMAS KWANTWI 4/28/2018

 BUS
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 Bus is the mechanism by which the CPU

communicates with memory and I/O devices
 Bus is not just a collection of wires
 Bus defines the protocol for communication
 Shared communication link
 Single set of wires used to connect multiple
subsystems
 A bus is also a fundamental tool for composing large,
complex systems

Created by Mr. THOMAS KWANTWI 4/28/2018

 Bus
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Created by Mr. THOMAS KWANTWI 4/28/2018

 What defines a bus?
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Transaction Protocol

Timing and Signaling Specification

Bunch of Wires

Electrical Specification

Physical/Mechanical Characteristics- the

connectors
Created by Mr. THOMAS KWANTWI 4/28/2018
 Generic bus structure
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 Address
 Data
 Control

Created by Mr. THOMAS KWANTWI 4/28/2018

 Generic Organization of a Bus
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 Control lines:
 Signal requests and acknowledgements
 Indicate what type of information is on the data lines
 Data lines carry information between the source and
the destination:
 Data and Addresses
 Complex commands

Created by Mr. THOMAS KWANTWI 4/28/2018

 Bus Characteristics
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 Bus signals are usually tri-stated

 Address and data lines may be multiplexed
 Every device on the bus must be able to drive the
maximum bus load:
 Bus wires
 Other bus drives
 Bus may include clock signal
 Timing is relative to clock

Created by Mr. THOMAS KWANTWI 4/28/2018

 Increasing the Bus Bandwidth
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 Non-multiplexed address and data lines:

 Address and data can be transmitted in one bus cycle if separate
address and data lines are available
 Cost (a) more bus lines, (b) increased complexity
 Data bus width:
 By increasing the width of the bus, transfers of multiple words
require fewer bus cycles
 Cost: more bus lines
 Block transfers:
 Allow the bus to transfer multiple words in block-to-block bus
cycles
 Only one address needs to be sent at the beginning
 The bus is not released until the last word is transferred
 Cost: (a) increased complexity
 (b) decreased response time for request

Created by Mr. THOMAS KWANTWI 4/28/2018

 Advantages of Bus
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 Versatility:
 New devices can be added easily
 Low cost:
 A single set of wires is shared in multiple ways

Created by Mr. THOMAS KWANTWI 4/28/2018

 Disadvantages of Bus
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 It creates a communication bottleneck

 The bandwidth of the bus can limit the maximum
I/O throughput
 The maximum bus speed is largely limited by:
 The length of the bus
 The number of devices on the bus
 The need to support a range of devices with:
o Widely varying latencies
o Widely varying data transfer rates

Created by Mr. THOMAS KWANTWI 4/28/2018

 Parallel communication
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 Multiple data, control, and possibly power wires

 One bit per wire
 High data throughput with short distances
 Typically used when connecting devices on same IC or
same circuit board
 Bus must be kept short
o Long parallel wires result in high capacitance values
which require more time to charge/discharge
o Data misalignment between wires increases as length
increase
 Higher cost, bulky

Created by Mr. THOMAS KWANTWI 4/28/2018

 Serial communication
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 Single data wire, possible also control and power wires

 Words transmitted one bit at a time
 Higher data throughput with long distances
 Less average capacitance, so more bits per unit of time
 Cheaper, less bulky
 More complex interfacing logic and communication
protocol
 Sender needs to decompose word into bits
 Receiver needs to recompose bits into word
 Control signals often sent on same wire as data
increasing protocol complexity

Created by Mr. THOMAS KWANTWI 4/28/2018

 Synchronous Bus
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 Includes a clock in the control lines

 A fixed protocol for communication that is relative to
the clock
 Advantages: involves very little logic and can run
very fast
 Disadvantages:
 Every device on the bus must run at the same clock
rate
 To avoid clock skew, they cannot be long if they are
fast
 Most processor-memory buses
Created by Mr. THOMAS KWANTWI 4/28/2018
 Asynchronous Bus
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 Asynchronous Bus:
 It is not clocked
 It can accommodate a wide range of devices
 It can be lengthened without worrying about clock
skew
 It requires a handshaking protocol

Created by Mr. THOMAS KWANTWI 4/28/2018

 Basic Protocol Concepts
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 A bus transaction includes two parts:

 Issuing the command (and address)- request
 Transferring the data – action
 Master is the one who starts the bus transaction by:
 Issuing the command (and address)
 Slave is the one who responds to the address by:
 Sending data to the master if the master ask for data
 Receiving data from the master if the master wants
to send data

Created by Mr. THOMAS KWANTWI 4/28/2018

 Bus Arbitration
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 One of the most important issues in bus design:

 How is the bus reserved by a device that wishes to use it?
 Master –slave arrangement:
 Only the bus master can control access to the bus:
it initiates and controls all bus requests
 A slave responds to read and write requests
 The simplest system:
 Processor is the only bus master
 All bus requests must be controlled by the processor
 Major drawback: the processor is involved in every
transaction

Created by Mr. THOMAS KWANTWI 4/28/2018

 Direct memory access
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 Direct transfer of data by-passing CPU

 Using DMA controller
 Separate single-purpose processor
 Microprocessor relinquishes control of system bus to
DMA controller
 Microprocessor can meanwhile execute its regular
program
o No inefficient storing and restoring state due to ISR call
o Regular program need not wait unless it requires the
system bus
o Harvard architecture –processor can fetch and execute
instructions as long as they don’t access data memory if
they do, processor stalls
Created by Mr. THOMAS KWANTWI 4/28/2018