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HDI Image Transfer

Technology and Trend


志聖工業 高啟清博士
Charles Kao, Ph.D
Tel: 02-2601-0700
Fax: 02-2602-1556
Mobile: 0939-268-725
V2.1
cckao@csun.com.tw 2007/5/8
課程綱要
1. HDI Development 發展
2. HDI Structure 結構
3. HDI Major Process 製程
4. Fine Line Formation 技術課題
5. PCB 影像移轉設備發展現況

2004/4/15 2/80
HDI Development
From through to blind via
Methods to Increase PCB Density
1. Reduce hole and pad diameters
– More space for routing
– Increase cost, Process difficulty
2. Reduce conductor width
– More channels between pads
– Will increase cost, reduce board yield
3. Increase signal planes
– More layers of PCBs
– Increase cost
4. Use embedded passives
– Increase surface area, reduce routing
– Increase cost, Hadco/Sanmina patent issue
2004/4/15 4/80
HDI (Build-up) Definition
• High Density Interconnect ---
• 使用 Mircovia 微孔技術的電路板
– 孔徑 6 mil (150 µm)
– IPC/JPCA-2315 Design Guide for HDI and Microvia

• Purpose of HDI
– More circuit, more via on smaller PCB

• Design rule comparison HDI to MLB

2004/4/15 5/80
Electronic Assembly with HDI/Microvia

2004/4/15 6/80
Motorola Mobile phone Development
• Lighter, Thinner, • Sequential lamination
Shorter, Smaller to form blind and
輕薄短小 buried via
• High frequency, High • Laser drill to form
speed, Multi function blind via
高頻 , 高速 , 多功能 • 2 layer laser vias

2004/4/15 7/80
HDI Applications – Miniaturization
• Application – Camcorder
– cellular phone, L/S: 65/65~75/75
camcorder, notebook, Via/Pad: 150/250
PDA, GPS
– 6~10 layer
1~2 buildup layers
– Need PTH, IVH, BVH – Notebook PC
– Cellular phone L/S 75/75~100/100
L/S: 65/65~75/75 Via/Pad:
Via/Pad: 150/250 125~200/250~400

Source: PCFab 1999/9, TechSearch


2004/4/15 8/80
HDI Applications – IC Substrates
• Package substrate • Microvia IC Substrate
– Flip Chip, BGA, CSP, – MPU
MCM, Hybrid L/S: 70/70
– 6~12 layer, Via/Pad: 86/125
1~3 buildup layers – ASIC
– 需要 IVH, BVH Via/Pad: 75/150
– 避免使用 PTH,
PTH⇒
IVH+BVH

2004/4/15
Source: PCFab 1999/9, TechSearch 9/80
HDI Application - High Layer Count
• Application • Ibiden 1-12-1
– Router, Server, Base
station, Workstation,
Networking
– 14~24, up to 32 layers,
t=80~180 mil, up to 7.6 mm • Ibiden 1-20-1
– 1~2, up to 3 buildup layers
– PTH, Aspect ratio 12:1
– BVH, laser via
– Low Dk=3.4
– Low Df = 0.005
– Impedance ±8%
2004/4/15 10/80
Embedded Passives
• Embedded Resister • Buried Capacitor
– Termination resistor – De-coupling, LC filter
– Vcc - BC - GND
– 在 Power/Ground 間

• Inductor
– LC filter

2004/4/15 11/80
PCB Product Market Status

• Micro via PCB and IC substrate will accounts


25% of market value in 2007

Source: Prismark, 2003


2004/4/15 12/80
PCB 產品一般規格需求
PCB 類別 線寬 / 線 最小孔徑 環徑 對位精度

Card/Module 6~8 mil 0.3 mm + 5 mil 2 mil/50µm
>150 µm
Desktop PC 5/5 mil 0.3 mm + 5 mil 2 mil/50µm
125 µm
Notebook 板 4/4 mil 0.25 mm + 3 mil 1.2 mil/30µm
100 µm
HDI 手機板 3/3 mil 0.25 mm + 3 mil 1 mil/25µm
75 µm 盲孔 150 µ
BGA 載板 2/2 mil 0.25mmm + 2 mil 0.8 mil/20µm
50 µm
Flip chip 載板 1/1 mil 盲孔 75µm + 1 mil 0.4 mil/10µm
25 µm
2004/4/15 13/80
HDI Roadmap - Ibiden

Source: www.ibiden.co.jp
2004/4/15 14/80
HDI PCB 結構
(Build-up/HDI PCB)
多層板結構
線寬
Conductor Width
孔環
外層線路 Annular Ring
線距
Conductor Space
孔徑

內層 1
Inner
Layer #1

內層 2
Inner
內層線路 Layer #2
盲孔 通孔
Blind Via 埋孔 Through Hole
Buried Via
絕緣介質層
Dielectric 增層法多層板 傳統多層板
Build-up PCB Multi Layer PCB
2004/4/15 16/80
Buildup PCB Structure
• Buildup PCB 結構 • 導通孔型式演進
– 芯層 Core – Multi-layer PTH 通孔
– 絕緣層 – Sequential lamination
Buildup Dielectric blind/buried via
– 盲埋孔 – 1 Layer blind via
Blind / Buried – 2 Layer blind via
Via • Staggered Via
• Buildup PCB 表示法 • Skipped Via
• Stacked Via
– Face Buildup 層數
+ Core 層數 – Via on PTH
+ – Via in Via
Back Buildup 層數
– 例 : 1+4+1, 2+2+2,
2004/4/15 17/80
Multi-layer Blind Via Configuration

* Stacked Via
* Staggered Via
3 Level
* Skipped Via
L1-L3

* Stacked Via
L1-L2-L3
2004/4/15 18/80
Advanced Microvia Configuration

• Via on PTH
– 塞孔不能凹陷
– 注意 Peeling Strength 不
足 • Cu Filled Via
• Via in via – IC Substrate 上 Flip
– For Flip chip substrate Chip 焊墊
2004/4/15
signal shielding
19/80
Via and Pad
• Via off Pad
– Traditional fan out
circuit required
• Via in Pad
– No Fan Out circuit
– Microvia on side of
• Save space SMT pad
• Reduce routing • Via on Pad
– Microvia under pad

2004/4/15 20/80
HDI Type I Structure
• Type I:
– 1-C-1, one micro via
layer per side (BVH)
– No buried vias
• Application

• Process

Design spec

Source: www.ibidenusa.com

2004/4/15 21/80
HDI Type II Structure -2
• Type II:
– 1-C-C-1, One micro
via layer per side
– 2 IVH (Inner Via Hole)
• Application

• Process

Design spec

2004/4/15 22/80
HDI Type III Structure
• Type III:
– 2-C-2, staggered micro
via
– Stacked via
– IVH

• Application
• Process

Design spec

2004/4/15 23/80
HDI Type IV Structure
• Microvia layers used
as RDL over predrilled
passive substrate

2004/4/15 24/80
HDI Type V Structure
• Type V:
– Even number of layers
– Coreless
– Plated microvia and
conductive paste
interconnections
– One lamination
– Ex. ALIVH/Panasonic

2004/4/15 25/80
HDI Type VI Structure
• Type VI:
– Electrical
interconnection and
mechanical structure
are formed
simultaneously
– Ex. B2it/Toshiba

2004/4/15 26/80
HDI
Major Process
Buildup/HDI PCB 製作主要流程
• 內層 Core 製作
– 標準多層板製程
– 埋孔塞孔製程
• Buildup 層製作
– 增層製程
– 盲孔製程
• Cu windowing 開銅窗 : 曝光
• Laser via 雷射盲孔
• Cu plating 盲孔電鍍
– 外層線路製程 : 曝光
• 表面處理
– 防焊製程 : 曝光
2004/4/15
– 選擇性鍍金製程
28/80
Buildup Material & Process Category
Sequential Buildup

Dielectric Format Via Formation Metallization Method

Material Via Plating/Circuit


Coated Foil
* Reinforced Laser Drilling Additive Plating
* Non-reinforced

Conventional Photoimaging Semi-Additive Plating


Reinforced Laminate
*Woven *Non-woven
Dry or Wet Etch Subtractive
Liquid * Plasma
* Photoimageable * Caustic
Conductive Paste
* Non-photoimageable

Mechanical
Dry Film Source: The Board Authority 2000/3
* Drilling
* Photoimageable
* Punching * Piercing
* Non-photoimageable
2004/4/15 29/80
Dielectric Material
• Material • Equipment
– RCC / RCF 背膠銅箔 – RCF → 真空壓合
– FR4, BT Lamination
– Liquid Dielectric 液態 – Liquid → 垂直 Roller
• Taiyo, Ciba, ….. Coating
– Film Dielectric 乾膜 – Film → 真空壓膜機
• Ajinomoto, Hitachi Vacuum Laminator
– Aramid 聚醯胺 – Aramid → 真空壓合
• Dupont/Thermount Lamination

2004/4/15 30/80
Via Formation Methods

• Photovia • Plasmavia • Laservia • Pastevia


– IBM SLC – DYCOstrate – ALIVH
– B2it
2004/4/15 31/80
各式盲孔 Via 成孔比較
• Laser 雷射鑽孔 • Plasma 電漿蝕刻
– CO2 Blind Via: 150µm – Through Hole: 60µm

– Blind Via: 100µm


• Photo 曝光成孔
– Blind Via: 150µm

• Mechanical 機械鑽孔
– Blind Via: 100µm

2004/4/15 32/80
IBM SLC - Photovia
• Surface Laminar
Circuit
• IBM Yasu (Japan)
• Process
– Photo-imageable
dielectric coating
– Via exposure
– Develop
– Via Cu plating
– Circuit formation

2004/4/15 33/80
Dycostrate - Plasmavia
• Dielectric lamination

• Via formation
– Cu Windowing →
Double-side Plasma
Etching
• Via Cu plating
• Circuit formation

Source: www.dyconex.com

2004/4/15 34/80
Laser Via on RCF, FR4, ABF
• Resin Coated Copper Foil
– Cu 12 µm
– Resin 35~70 µm
• Dielectric buildup
– FR4/RCC Lamination
→ Cure
• Via formation
– Cu windowing →
CO2 Laser Drilling
– UV Laser direct drilling
• Via Cu plating
2004/4/15 35/80
• Outer layer circuit process
Conformal Mask Laser Via Process
1.Buildup layer lamination 1.Laser drilling
– RCC – CO2 laser driller
– FR-4 2.Desmear
2.Skiving – Plasma desmear
– Expose alignment target – Wet desmear
in inner layer
3.Electroless Cu
3.Conformal mask – Horizontal line
– Exposure Cu window
4.Cu panel plating
– Etch Cu window
– Horizontal PRP plating
5.Outer layer circuit

2004/4/15 36/80
Matsushita ALIVH Process
• Non-woven Aramid
聚醯胺
• Prepreg via formation
– Laser Drilling
• Conductive paste via
filling
• Lamination
• Circuit process

2004/4/15 37/80
Toshiba B2it Process
• Conductive piercing
cone printing
• PP piercing
• Layer lamination
• Circuit process

2004/4/15 38/80
Fine Line Formation
1. Thin Copper
2. Fine Line Exposure
3. Fine Line Etching
Effect of Pitch on L/S
• Laser Via channel • Pitch 1.27 mm (48 mil)
– Via+ring = φ20 mil
– Max. 3 line per channel
– Line width
= (48-20) / 7 = 4 mil
• Pitch 0.737 mm
– Line width
= (0.737 – 0.35) / 5 ≈ 3
• CSP fanout mil
• Pitch 0.8 mm
– 100 µm line x 1
– 60 µm line x 2
• Pitch 0.5 mm
2004/4/15 40/80 – 50 µm line x 1
Fine Line Process Key Issues
• L/S Requirement 1. Thin Copper 薄銅
– HDI: 3/3, 2.5/2.5 mil 2. Fine Line Lithography
– BGA, CSP, FC: 50/50, 細線曝光
35/35, 25/25 µm – L/S Resolution 解析度
– Impedance control L/S • Collimation angle
∀ ±15% , ±10% • Energy uniformity
• Etching Factor – Overlay registration
Accuracy 對位精度
3. Fine Line Etching
細線蝕刻
– Uniformity
– Etching factor
2004/4/15 41/80
Copper Foil Thickness and Profile
• 銅箔 (Copper Foil):
– 重量 厚度
.
– E (5 µm) (0.20 mil, 5 µm)
– Q (9 µm) (0.34 mil, 9 µm)
– T (12 µm) (0.47 mil, 12 µm)
– H oz/ft2 (153 g/m2) 0.5 oz (0.7 mil, 18 µm)
• Foil Profile
– Standard: n/a
– Low profile (L): max. 10.2 µm = 400 µin profile
– Very-low profile (V): max. 5.1 µm = 200 µin profile

2004/4/15 42/80
Subtractive and SAP Process
• Subtractive (L=50~35 µm)
• Laminate Cu (T oz, 12 µm)
• Laminate 2-ply ultra-thin
Cu foil (3~5 µm)
then → dry film
→ exposure → plating
subtractive etching
• Semi-Additive Process:
Lamination (L=25 µm)
– Laminate Cu (12 µm) foil
→ Flush etch Cu to 8 µm
→ dry film → exposure →
plating Cu/Sn → etching
2004/4/15 43/80
SAP and Additive Process
• Semi-Additive Process:
Thin Film (L=18 µm)
• Deposit electroless Cu
→ dry film → exposure
→ pattern plating Cu/Sn
→ etching Cu
→ strip Sn

• Fully Additive (L=10 µm)


• Form circuit using all
electroless Cu

2004/4/15 44/80
Etch Progression
• Etch 3/3 on 1 oz Cu
– Undercut = (R-T)/2
– Etch factor=2t/(B-T)

Etch Undercut Etch Extend of


time factor etch
90 s 0.05 mil 0.90 0.5
110 s 0.30 1.75 0.75
125 s 0.45 2.33 1.1
140 s 0.525 2.67 1.0
165 s 0.75 3.11 1.25

2004/4/15 45/80
Fine Line Etching
• Artwork • Etching
– Finer DPI – Acid etch has better
• Exposure etching factor
– Collimation – Uniformity
– Uniformity – Compensation design

• Developing
– Uniformity
– Reduce puddle effect
• Cu foil thickness
– Uniformity:
½ oz Cu 17±1 µm
2004/4/15 46/80
目前 PCB 外層板曝光製程課題
課題項目 影響因素
1. 解析度 Resolution 1. 光學能力
線寬 / 線距 Line 平行光角度 CHA/DA
width/Line space 曝光能量均勻性
線寬公差 Tolerance Uniformity(%)
2. 對準度側蝕 Undercut
Registration Etching factor
2. 對位能力
對位精度 Alignment 曝光機對位精度
accuracy X-Ray 鑽靶精度 1 mil
層間對位 Inter-layer 機械鑽孔精度 2 mil
registration
3. 尺寸安定性 Dimensional 3. 環控能力
Stability 鑽孔位置精度 Drilling PCB 漲縮 500 ppm
accuracy
板材漲縮 PCB distortion Mylar 片 18 ppm/1°C, 9 ppm/%RH
4. 生產性底片漲縮 Mask distortion
Productivity/Yield 4. 生產能力
適用薄板尺寸 薄板傳送 ,Contact free,
Particle free
2004/4/15產能 Throughput 47/80
Resolution and Uniformity
• Fine Line Process • 全影 半影區
– Thin copper treating • Photoinitiator 反應率
– Fine line exposure and – 30~50% used after exp
alignment
• Monomer 反應率
– Fine line etch
• Uniformity
• 玻璃光罩 Glass
Photo Mask
• 高精度 , Partition,
Stepper 曝光機

2004/4/15 48/80
底片繪圖機 Photo Plotter
• Barco Silver Writer • 解析度 Resolution
– 4,000~25,400 dpi
• 對準度 Registration
– 設備
• Accuracy 0.16 mil/4µm
• Repeatability 0.08 mil/2 µm
• For Mylar/emulsion – 轉移至底片上
• Laser 光源 • Accuracy 0.5 mil/12.5 µm
• Repeatability 0.5 mil/12.5 µm
– Helium-Neon 633 nm
– Red laser diode 670 nm
• 產能 PCB 18"x24“
– 4000 dpi, 2 min/pcs
– 20,000 dpi, 10 min/pcs
2004/4/15 49/80
光罩繪圖機 Mask Generator
• Heidelberg • 解析度 Resolution
Mask Write 800 – Resolution:
50, 125, 250, 500 nm
– Min. feature:
0.8, 1.7, 3.5, 8 µm

• For • 對準度 Registration


– Glass/Chrome – Interferometer: 40 nm
– Glass/emulsion – Overlay Accuracy 250 nm
– Mylar/emulsion • 產能 Throughput
• Laser 光源 – PCB 18"x22", 50,000 dpi,
35 min/pcs
– Nd:Yag 532 nm
– Argon-ion 363 nm
2004/4/15 50/80
Photo Mask (Artwork) Error
• 曝光底片種類 • 底片漲縮參數
– 偶氮 (Diazo 棕片 ) – Kodak Accumax ARX7
• Solder mask, circuit – 底片厚度 7 mil
– 鹵化銀 (Emulsion 黑白片 ) – 溫度 : 0.0018% / °C
• Circuit, solder mask
– 溼度 : 0.0009% / %RH
– 玻璃底片 (Photo Mask) for
• 底片補償
fine paten exposure
• Soda lime w/ emulsion, chrome – 壓合經緯向補償
– cheap • Ex. X: 1.000225
• Borosilicate w/ chrome • Ex. Y: 1.000625
– Low expansion glass – 蝕刻製程補償
• Quartz w/ chrome • Ex. 內層 L/S:
– Highest quality 曝光 4.5/3.5→ 蝕刻後
4/4
2004/4/15 51/80
Mylar Artwork & Photo Mask 比較
Mylar Mask
CTE (° 18 ppm
C)
CHE 9 ppm
(%)
OD >4.5
CD 6 µm 0.8 µm Mylar/
Diazo
Mylar/
Emulsion
Edge
roughness

Glass/
Emulsion

2004/4/15 52/80
Effect of DPI on Fine Pattern Plotting
DPI µm/dot 75µm 50µm 25µm 20µm 15µm 10µm
4,000 6.35 16.9% 25.0% 50.0% 63.5% 84.7% n/a

6,000 4.23 11.3% 16.9% 33.8% 42.3% 56.4% 84.6%


8,000 3.17 8.5% 12.7% 25.4% 31.7% 42.3% 63.5%

12,700 2.00 5.3% 8.0% 16.0% 20.0% 26.7% 40.0%

20,000 1.27 3.4% 5.0% 10.0% 12.7% 16.9% 25.4%

25,400 1.00 2.7% 4.0% 8.0% 10.0% 13.3% 20.0%

50,000 0.50 1.3% 2.0% 4.0% 5.0% 6.7% 10.0%

Based on 10% line width


2004/4/15 53/80
Photo Resist Development
• Fine line dry film resist • Ex. Dupont dry film
– Dry Film Components – USF < 1 mil, 120~150 mj
– Dupont, Asahi, NIT – SF >1 mil
– 1/1 for outer layer plating – FX > 2 mil
• Liquid photo resist – R > 3 mil, 50~60 mj
• Regular: 6±2steps: ±0.2 mil
– Thickness: 10~12 µm
– 3/3 for inner layer etching – APFX > 4 mil, 20 mj, for
inner layer use
• Electrical Deposited resist – Exposure energy for fine
– Nippon Paint line film is much higher than
– Positive liquid resist normal film
– Landless Design – Ultra fine: no change in
energy range
2004/4/15 54/80
Registration Methods and Error Budget
• Registration – Skiing 曝光
– Via annular ring • 開內層對位靶天窗

– Solder mask opening – Conformal mask 曝光


• 開雷射銅窗
– Alignment method
• Global alignment
– Pad to laser via
• Local alignment – Pad to PTH
• Group mark alignment – 環與孔對準
• Registration
• 4 point Alignment
• Alignment mark
recognition ability

2004/4/15 55/80
PCB Material Distortion
Layer 2 - Post Bond Distortion Model (Stretch Layer 2 - Post Bond Distortion Model (Stretch Layer 2 - Post Bond Distortion Model (Stretch
Adjusted) Adjusted)
Adjusted)

400 400

400
300 300
300
200 200
200
100 100
100
0 0
0

-100 -100 -100

-200 -200 -200

-300 -300
-300

-400
-400 -400
-400 -300 -200 -100 0 100 200 300 400 -400 -300 -200 -100 0 100 200 300 400 -400 -200 0 200 400

With 1080 With Thermount With 2113


Fabric (DuPont) Fabric

• Varies with material


• Varies with panel size
• Inconsistent from panel to panel

Source: Viasystems

2004/4/15 56/80
PCB 影像移轉設備
發展現況
IC/LCD/PCB 成像技術比較
產業別 IC TFT LCD STN LCD PCB
曝光方式 Step & Scan Step & Repeat Off-contact Contact
Projection Projection Proximity Exposure
曝光面積 25x33mm 120x120mm 356x406mm 535x610mm
線路解析度 0.13 µm 2.4 µm 8~10 µm 20 µm
光阻 CVD CVD/PVD Roller coat Dry Film
塗佈方式 /Spin coat Lamination
膜厚 0.06 µm 0.8 µm 1.2~1.5 µm 20 µm
線路 / 膜厚 2:1 3:1 6:1 1:1

Mask 材質 Quartz Quartz Glass Mylar
工作物 Silicon Wafer Glass Glass Cu+Epoxy+Fiber
環境要求 Class 1 Class 10 Class 100 Class 1000
全球有此能 > 20 Standard Standard < 10
力廠商 20~30% < 1%
2004/4/15 58/80
PCB 影像移轉方式的演進
• 線路抗電鍍 / 蝕刻阻劑形
成方式的演進 • 接觸式分割曝光
Partition
進階影像移轉方法
• 投影式曝光 Stepper
• 雷射直接成像 LDI
• 雷射燒除成線 LDS
解決方案
• 平行光曝光 (2
接觸式曝光法
mil)
• 散射光曝光 (5 ?
• 網版印刷 (8 mil)
mil)
傳統印刷電路板
2004/4/15 59/80
進階影像移轉解決方案
• Optical Exposure Technology • Laser Scanning Technology
• Contact Printing (Non-Optics Technology)
接觸式曝光 • Laser Direct Imaging
– Collimated exposure 雷射直接成像
– Mask compensation (sorting) – Laser direct imaging
– Partition exposure – Thermal laser direct
• Projection Imaging imaging
投影式曝光 • Laser Ablation
– Step and repeat 雷射燒除成線
– Step and scan – Laser structuring
– Laser projection imaging – Laser patterning
– Projection with dynamic mask
2004/4/15 60/80
接觸式曝光原理 Contact Printing
• 使底片與 PCB 光阻 • 優勢
密貼後曝光 – 既有成熟技術
• Collimated exposure – 設備供應商多
– 光垂直 , 減少側蝕 – 設備成本較低
• Mask compensation – 產能大
– 量測 PCB 重要尺寸 , • 劣勢
在底片上補償 – 良率
• Partition exposure – 無法做板面漲縮補償
– 分區曝光 , 把不曝光 – 大面積接觸不均勻影
部分遮住 響解析度
– 底片損傷
– Particle 污染
2004/4/15 61/80
平行光曝光系統 Collimated
積光器 Exposure
(Integrator)

反射鏡 冷鏡
(Reflection Mirror) (Dichroic Mirror)

曝光照射面 橢圓集光器
(Exposure Surface) (Collector)

平行反射鏡 點光源短弧燈
(Collimation Mirror) (Short Arc Lamp)

• 平行光源 : 5KW 汞氙短弧



• 平行半角 (CHA): 1.5°
• 斜射角 (DA) < 1°

2004/4/15 62/80
接觸式曝光發展現況
• 解析度 • 尺寸安定性 issue
– 光阻 – PCB
• 較薄乾膜光阻 0.6 mil • 薄板漲縮嚴重
• 正型光阻 – 底片
– 提高曝光均勻度至 • Low expansion film
>90% • 使用玻璃光罩
– 使用半加成法製程可達 • 影響產能因素
L/S=20/20 µm – 四點對位 退率高
• 對準度 – 板材漲縮使 退率高
– 四角 Global alignment – 預先 sorting 費時
– 內部 Local alignment – 分割曝光 ,cycle time 倍
– 防焊 Fiducial alignment 增

2004/4/15 X-ray alignment 63/80
接觸式自動曝光機
• 內層雙面曝光
– L/S 1.5 mil
– 對位精度 : ± 20 µm
– 產能 : 4 pnl/min
• 外層單面曝光
– L/S 1.5 mil
– 對位精度 : ± 10 µm
– 產能 : 3 pnl/min
• 防焊單面曝光
– 對位精度 : ± 10 µm
– 產能 : 2 pnl/min
2004/4/15 64/80
分割曝光 ADTec SRP-600
• 小光罩分割曝光 • CCD cameras for
– 4~16 steps alignment retract prior
• L/S 20 µm to exposure.
• Alignment: ±2µm • Stage 1 is an
• 正中曝光 alignment stage with
movable X, Y, and θ.
• Stage 2 is a step &
repeat stage with
movable X and Y.

2004/4/15 65/80
分割曝光 ADTec ACP-630
• 大光罩分割曝光
• Local Alignment: ±5µm
• 不可 scale, 留邊大
• 浪費有效曝光區
• 希望發展正中曝光提昇效率

2004/4/15 66/80
投影式曝光原理 Projection
Imaging
• 步進曝光:一次一格
• Local alignment 對位
• 鏡組可等比例尺寸縮
放補償
• 餘光少 , 所需留邊小

• 光學鏡組將光罩 (8)
上影像投影至
PCB(10) 上

2004/4/15
Source: www.ushio.co.jp 67/80
投影式曝光發展現況
• 曝光解析度 • 優勢
– 7~12 µ m – 光罩不接觸板面良率高
• 對位精度 – 光罩與板面對位精準
– Alignment ± 2~3 µm – 可做漲縮補償
• 尺寸安定性 – 可用標準光阻劑
– 底片使用玻璃光罩 – 不需留邊
– 適用防焊曝光
• 產能
• 劣勢
– Step & Repeat 降低產能
– 最大曝光面積 5~6"
– X 及 Y 方向補償 相同
– 光罩製作
2004/4/15 68/80
Step & Repeat 曝光機 Ushio UX-
5038

• 曝光 Step & Repeat • 解析度


– 光源 2 KW Short Arc – L/S : 12 µm
– 曝光強度 35 mw/cm2 – DoF: ± 50 µm
– 均勻度 5% • 對準度
– 曝光面積 : 正方 , – On-axis 2 CCD alignment
Max. 141 x 141 mm – Overlay accuracy: ± 6.5 µm
– Scaling: ± 1000 ppm
2004/4/15
Source: www.ushio.co.jp 69/80
Step & Scan 曝光機 Tamarak Model 302

• 曝光 Scanning • 解析度 :
– 光源 1 KW Short Arc – L/S: 4 µm
– 曝光強度 40 mw/cm2 – DoF: 30 µm
– 均勻度 3% • 對準度
– Scan 面積 : – Alignment 精度 : ± 2 µm
長方 200 mm

2004/4/15
Source:www.tamsci.com 70/80
雷射投影成像 Laser Projection
Imaging
• Anvik HexScan 2100SPE
– Excimer UV Laser 351 nm,
45~75 mw/cm2
– HexScan 40 x 40 mm 拼圖
– 投影至光阻上掃描曝光
– 線路 structuring
• 解析度
– L/S: 10/10 µm
• 對準度
– Accuracy: ± 2.5 µm
• 產能
– 120 pnl/hr
2004/4/15 71/80
Projection with Dynamic Mask
• Ball semiconductor
(Japan)
• TI

2004/4/15 72/80
雷射直接成像 Laser Direct Imaging
• PCB 壓高感度 (5mj) 雷射乾

• 線路 CAM 資料傳至機台
• 檢查 PCB 板各對位 點位置
• 計算漲縮補償值
– Global compensation
– Local compensation
• Ar or UV 雷射掃描使乾膜
曝光
• 作第二面對位曝光
• 顯影蝕刻製作線路
2004/4/15 73/80
雷射直接成像發展現況
• 設備類型 • 優勢
– UV Laser – 不需底片製作
– IR 熱感 Laser – 對位較準
• 精度 Accuracy – 可做獨立 X 及 Y 方向補償
– 線路定位精度 – 每片板有識別編號
– 雙面對位精度 – 適合打樣或小量生產
– 重置精度 • 劣勢
• 聚焦深度 Depth-of-Focus – 單點曝光產能較低
• – 需使用特殊光阻劑 - 貴貴
自動補償 Scaling

• 接合經度 Strip-Butting – 線路解析度 2 mil→35 µm
• 光學元件效率 – 功率較低不適用綠漆曝光
2004/4/15 74/80
LDI 設備發展現況

廠牌 Pentax Etec Orbotech Automatech Barco Creo


機型 DI-2020 DigiRite 2000 DP-100 DI-2700 Gemini Diamond 5170F
水平單面 水平單面 水平單面 水平雙面 垂直雙面 滾筒式
雷射源 Ar UV laser UV laser Ar+, UV Solid-state UV IR laser
波長 (nm) 333 333~364 355 nm
雷射點 (μm) 15 5 方點
解析度 (μm) 5 6.3 6.3
最小線寬 (μm) 30 50 50 40 50 25
線寬公差 (μm) ± 10 ±5 ± 2.5
邊緣粗度 (μm) 5 5 ± 2.5
定位精度 (μm) ± 15 ± 12.7 ± 10 ±8 ± 12.7 ± 20
對位精度 (μm) ± 20 ± 20 ±5 ± 6.3
接合精度 (μm) ±5
有效面積 (mm) 340x600 610x762 610x810 610x762 613x810 493x711
產速 sec/side 26 30 30 20 30 72
340x250 457x610 457x610 457x610 457x610 457x610
2004/4/15 75/80
雷射直接成線發展現況
• 設備類型 • 雷射成線優勢
– 雷射成線 – 直接成線不需光罩
Laser – 可做漲縮補償
Structuring – 可用於雷射鑽孔
• Solid state UV laser,
Siemens • 雷射投影成線優勢
• THG UV laser: LPKF – 光罩不接觸板面良率高
– 雷射投影成線 – 可做漲縮補償
Laser – 可用於雷射鑽孔
Projection Imaging
• Excimer laser ablation: • 劣勢
Anvik, Tamarak – 新科技
– 單一供應商
2004/4/15 76/80
雷射成線系統 Laser Direct Structuring
• Siemens Microbeam 系統
• 直接用 Laser 掃描,依照工程資料將 PCB 表面
錫抗蝕刻阻劑燒除,再蝕刻後完成線路
• 適用用於 IC Substrate 、 HDI PCB 、 Lead
Frame 局部細線路製作
• 雷射源
– Nd doped, 1064 nm, diode pump
– UV 532 nm, 355 nm
• 解析度
– L/S - 50/50 µm
• 對準度
– Accuracy: 10 µm
2004/4/15
Source: www.pl.siemens.de 77/80
雷射直接成線製程
• 全板鍍銅 • 線路蝕刻
Plate Cu Etch
– 10~15 µm Cu

• 全板浸鍍錫
Immersion Tin • 剝錫
Strip Tin
– Etch resist
– 1 µm Tin

• 表面處理
• 燒掉線路間錫材
Surface Finish
Laser ablation Tin
– 1000 mm/sec
2004/4/15
Source: www.pl.siemens.de 78/80
雷射成線 Laser Patterning
• LPKF MicroLine Drill 600
– THG UV Laser 355 nm
– Scan 60x60 mm
– 直接燒除銅層
• 用途
– 線路 structuring
– 綠漆 structuring
– 雷射鑽孔
• 解析度
– L: 20 µm
• 對準度
2004/4/15
Source: www.lpkfusa.com 79/80
– Accuracy: 15 µm
本單元結束

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