TIMERS

Monostable Multivibrators
• Monostable multivibrator – A switching circuit with
one stable output state.
– Also referred to as a one-shot.
– The one-shot produces a single output pulse when it
receives a valid input trigger signal.
 Monostable Operation

Figure 5 – 555 Timer Set Up for Monostable Operation

Stable State:
1. The output Qbar of the SR flip-flop (also called a RS flip-flop) is
initially set HIGH which turns on the discharge transistor. The
discharge transistor then grounds the capacitor C1. The outputs of
both comparators 1 and 2 are LOW. See Figure 6.

Initial Timing Chart

Figure 6 – C1 Grounded
Unstable State (C1 Charging):
2. Comparator 2 serves as the input S (Set) and comparator 1 serves
as the R input (Reset) into the SR flip-flop. With the THRESHOLD
grounded in the initial stable state, the output of non-inverting
comparator 1 is LOW. When the switch S1 is closed driving the
TRIGGER input to LOW (more precisely, when it drops below 1/3
Vcc), the output of lower inverting comparator 2 is driven HIGH (See
Figure 7). From the SR flip-flop truth table below (Table 1), when the
S input is HIGH and R is LOW, the output Qbar of the SR flip-flop is
driven LOW and the 555 timer OUTPUT is HIGH due to the inverting
buffer stage.

Table 1 – SR Flip-Flop Truth Table

 Figure 7 – C1 Charging Through R1

3. Since the Qbar is LOW, the discharge transistor is turned off and C1
begins charging through R1. See Figure 7.
4. The switch S1 is opened driving the TRIGGER back to HIGH (Figure 8).
The output of the lower comparator 2 changes to LOW (Vcc > 1/3 Vcc);
comparator 1 remains unchanged at LOW. The trigger pulse must be
shorter than the output pulse width allowing time for the timing capacitor
to charge and then discharge fully.

Figure 8 – C1 Continues Charging Through R1

5. From the SR flip-flop truth table, the output Qbar of the SR flip-flop does
not change (S=0 & R=0), thus remaining in a LOW state.
 Unstable State (C1 Discharging):
6. C1 continues to charge until the voltage across C1 exceeds 2/3 Vcc.
At this point, the upper comparator 1 is driven HIGH (Figure 9). From
Table 1, the SR flip-flop is driven to HIGH (S=0 & R=1) which turns on
the discharge transistor and grounds C1 again.

Figure 9 – When the Voltage across C1 > 2/3 VCC, C1 Is Grounded

 Return to the Stable State:
7. The voltage across C1 is greater than 2/3 Vcc for only a moment
before dropping below 2/3 Vcc driving the upper comparator 1 to
LOW (Figure 10).

Figure 10 – 555 Timer Returns to Stable State

8. From the SR flip-flop truth table, the output Qbar of the SR flip-flop does
not change (S=0 & R=0), thus remaining in a HIGH state and discharge
transistor continues to ground C1. The 555 will remain in the stable state
until another LOW trigger pulse is detected.
 Astable Multivibrators

• Astable multivibrator – A switching circuit that has no

stable output state.
– The astable multivibrator is a rectangular-wave oscillator.
– Also referred to as a free-running multivibrator.
 Astable Operation

Figure 3 – 555 Timer Set Up for Astable Operation

Charging:
1. When the power is turned on, capacitor C1 is not charged and pin 2
(TRIGGER) and pin 6 (THRESHOLD) voltage (Vin) is at 0 V.
2. The output of lower comparator 2 (inverting) is therefore HIGH (Vin <
1/3 Vcc) and the output of the upper comparator 1 (non-inverting) is
LOW (Vin < 2/3 Vcc).
3. Comparator 2 serves as input S (Set) and comparator 1 serves as the
R input (Reset) for the SR flip flop (also called a RS flip-flop). From
the truth table below for a SR flip-flop, S input is HIGH and R is LOW,
therefore the output Qbar of the SR flip-flop is LOW and the 555 timer
OUTPUT is HIGH due to the inverting buffer stage.

Table 1 – SR Flip-Flop Truth Table

4. Since Qbar is LOW, the discharge transistor is turned off and C1
begins charging through R1 and R2. While the capacitor C1 is
charging, the OUTPUT of the 555 timer is HIGH; while the capacitor
C1 is discharging, the OUTPUT of the 555 timer is LOW.

Figure 5 – C1 Charging Through R1 and R2

5. When the voltage across C1 (Vin) reaches 1/3 Vcc, the output of the
lower comparator 2 changes to LOW; comparator 1 remains
unchanged.
6. From the SR flip-flop truth table, the output Qbar of the SR flip-flop
does not change (S=0 & R=0), thus remaining in a LOW state.
7. C1 continues to charge until it reaches 2/3 Vcc. At this point, the
upper comparator 1 changes to a HIGH state.
8. Since the input R is HIGH and input S is LOW, the output Qbar of
the SR flip-flop goes to HIGH.
Discharging:
9. The HIGH output from the SR flip-flop turns on the discharge
transistor which creates a discharge path for C1 through R2.

Figure 8 – C1 Discharging Through R2

10. The discharge of C1 causes the output of the upper comparator 1
to change to LOW.
11. The output Qbar of the SR flip-flop does not change (S=0 & R=0),
thus remaining in a HIGH state.
12. When C1 discharges to 1/3 Vcc, the lower comparator 2 output
changes to HIGH causing the output Qbar of the RS flip-flop to go
LOW (S is HIGH and R is LOW). The LOW output Qbar from the SR
flip-flop turns off the discharge transistor and C1 begins to recharge.
13. The output of lower comparator 2 then changes to a LOW state, but
the RE flip-flop remains LOW continuing to charge the capacitor C1.
The capacitor continues the new recharge cycle.
14. The 555 timer repeats the charge/discharge cycle between 1/3 Vcc
and 2/3 Vcc producing an output periodic square wave (Figure 12).

Figure 12 – Relationship between Vin and the Output of the 555 Timer
Output Pulses and Formulas for Astable
Operation

555 Timer Output Pulses for Astable Operation

Figure 15: Astable Operation Circuit

Formulas:
Discharging time is given by (time of output in HIGH state):
T1 = TH = 0.693 (RA + RB) C
Discharge time is given by (time of output in LOW state):
T2 = TL = 0.693 RB C
Total period is:-
T = TH + TL
= 0.693(RA + 2RB)C
Output frequency :

% Duty cycle: D ( ratio of high state to period of pulse)

 Bistable Multivibrator
The circuit is called a bistable because it is
stable in two states: output high and output low.
It is also known as a 'flip-flop'.
It has two inputs:
– Trigger (555 pin 2) makes the output high.
Trigger is 'active low', it functions when
< 1/3 Vs.
– Reset (555 pin 4) makes the output low.
Reset is 'active low', it resets when < 0.7V.
Circuit diagram of 555 timer
bistable mode

555 bistable circuit

 Circuit operation
The circuit is two basic inverters,
each taking its input from the other's
output. When power is first applied,
Q1 turns on, its output will be a logic
0. This will be applied to Q2's input
resistor, keeping Q2 turned off so
that its output will be a logic 1. This
logic 1 will be applied back to Q1's
input resistor, keeping Q1 turned on
and holding the entire circuit locked
into this stable state.
On the other hand, if Q1 stays off at power-up, it will apply a
logic 1 to Q2's input, thus turning Q2 on. The resulting logic 0
output from Q2 will in turn hold Q1 off. The circuit will then
remain in this stable state indefinitely.
 Waveforms of bistable multivibrator

Notice that the circuit is symmetrical; that is, each

transistor amplifier has the same component values.
When power is first applied, the voltage divider
networks place a negative voltage at the bases of Q1
and Q2. Both transistors have forward bias and both
conduct.