Lecture-4

PHYSICS OF POWER DISSIPATION IN

CMOS DEVICE

Dr. Arti Noor

M. Tech (VLSI) Division, CDAC Noida UP.

27-1-2010, LPVD-Lecture-4
TOPICS :

•Low power VLSI design Limits.

•Principles of Low Power Design.

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 Low power VLSI design Limits.

• As per Moore’s law the growth in number

of transistors per chip becomes double
after every one and half year.
•This growth affects the reliability of chip.
•Power –delay product by transistor has
declined by a factor of 1/105.
•Because VLSI technology is a dominant
one in present era, there is much attention
on limitations which are not allowing
continuous scaling.
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 Principles of Low Power Design
• For low power design it is important to
understand the different aspects from
fundamental to practical consideration.

• There are three key principles for low power

design:
 Lowest supply voltage.
 Smallest size of device and thus
highest frequency
 Power management system.

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Hierarchy of Limits :
• Fundamental.
• Material.
• Device.
• Circuit.
• System.

• At each level two types of limits exist

 Theoretical consideration.
 Practical consideration.

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 Fundamental Limits

• Fundamental limits are independent of devices,

materials and circuits. They are derived from
basic principles of

 Thermodynamics.
 Quantum Mechanics.
 Electromagnetic.

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 Fundamental Limits
• Thermodynamics : Node N is imbedded in any chip.
Between N & G there is equivalent resistance R.
According to thermodynamic theory the mean square
open circuit voltage across R is en-2
• Available noise power is P
avail
• k = Boltzmann’s constant,
• T = absolute temperature,
• B = node bandwidth

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 Fundamental Limits
• Thermodynamics : If information at node N is changed
from 0-1 or 1-0, the average signal power Ps
transferred during switching should be greater than
Pavail by a factor  .
2
e 1 4kTBR 1
Ps  Pavail  n
  kTB; Es  kT
4 R 4 R
У≥1 is a constant
У = 4 recommended, so Ps must be > 0.104 eV .

Thus Es represents fundamental limits on binary

switching energy.

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Fundamental Limits :
• Quantum Mechanics :
Heisenberg Uncertainty Principle

– A measurable energy change E associated

with switching transition must satisfy the
condition

E ≥ h/ Δ t; h = Planck’s constant

– Thus required power during the transition is

– P ≥h / (Δt) 2

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Fundamental Limits :
• Electromagnetic Theory :
Velocity of high-speed pulse on an interconnect of
length L must always be less than c0 (speed of
light in free space):

•  is the interconnect transit time

L
 c0


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 Material limits
• Material and related properties :
– Carrier mobility, 
– Carrier saturation velocity vs.
– Thermal conductivity, K.
– Electric field strength .
– Material limit on switching energy can be
calculated as a energy stored on material
cube.
Vo
– Min switching time to store td 
v s Ec
charge. LPVD-Lecture-4
 Material limits
• Heat removal consideration : Fourier’s Law of heat
conduction
• Assume device is residing in ideal sink then power or
rate of heat transfer from device to sink

– P = Q/td = -KA dT/dx = p K ss T td

– K = thermal conductivity of semiconductor, A = surface area
of heat flow, T = temperature gradient
– For Si, td/P = 0.21 ns/W
– For GaAs, = 0.69 ns/W (unsuitable)
– There is speed advantage but it needs to conduct away three
times heat for the same transition time.
– Interconnect material limit
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 Device limits

• Effective channel length is important parameter.

Reduction in L causes second order effects in
device (short channel and leakage current due to
low Vt).
• Oxide layer thickness is other parameter for
controlling short channel effects as shown by Vt
shift expression.

• MOSFET leakage current and reliability are

effected by punchthrough, impact ionization.

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 Device limits

• Minimum effective channel length Lmin gives limit on

switching energy
– E = P td = P(Lmin/vsat)
– Min td between material and device limits case : the
difference is small
• MOSFET already pushing against Si material limits
• Limit on interconnect of length L, RC response time:
– Driven by a unit step voltage source, thus 0 to 90 %
response time
– t = RC = (ρ/Hr)(ε/He)L2

– ρ / Hr = sheet resistance, ε / He = sheet capacitance

– This specifies limit on minimum interconnect response
time t of given L. LPVD-Lecture-4
 Circuit limits

• Independent of architecture.
• Four circuit limits:

• First is to be able to distinguish ‘0’ and ‘1’ logic

level with almost zero error is basic requirement.
• A CMOS inverter can satisfy this requirement if
Vdd is > a minimum limit.
– Vdd>Vdd,min = β (kT/q) with β = 2-4.
– Vdd,min=0.1V at T =300 K.
• In practice this value can not be used because of
Vt. If Vt is very small, drain leakage current will be
very large. 1V is acceptable value.
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 Circuit limits

• Second limit is switching energy per transition.

This puts limit on minimum feature size. E = ½ C
V2 = P td

• Third is gate delay. i.e. time taken to

charge/discharge the load.
• P= E/ td , this puts limit on power consumption
during a transition or duration of transition puts
limit on P.

• Fourth is related to RC network model of wire.

The circuit is designed that RW< 2.3 Rtr.

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 System limits

• Five basic limits:

• Architecture limit.
• Power-delay product limit.
• Heat removal capacity limit
• Clock frequency limit
• Physical size limit.

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 System limits
• To consider these limit select one architecture of which
has 2D array.
• Same size macros with unskewed clock.
• Number of signal lines entering or exiting the macro cell
puts limit on transistor packing density.

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 System limits

• Power-delay product limit.

• Switching energy limit is defined by composite

gates that is characterized by critical path within
a macro cell.
• This critical path includes total wire length from
one corner to other corner.
• This gives total C, switching energy and
propagation delay.
• The average power dissipation is calculated
during the propagation delay.

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 System limits

• Heat removal capacity limit

• System heat removal is defined as average power

dissipation must be less than cooling capacity of
a composite gate P<QA.

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 System limits

• Clock frequency limit

• Number of gates on critical path puts limit on
clock frequency.

• Physical size limit.

• The allowable design space for a macro cell
depends :
-minimum achievable propagation delay,
-lowest gate switching power.
-largest minimum feature or chip size.
-heat removal system.
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 Practical limits

• The basis for practical limit is the opinion beyond

certain point in scaling, cost of designing,
manufacturing, and packaging will cause an
increase in cost.
• For further analysis Number of transistors per
chip is defined as.
• N= F-2 D2 PE
• F is minimum feature size, D is chip area and PE
is packaging efficiency.
• One has to calculate N for optimistic prediction
which ensures that chip is economically viable in
addition to technically possible.

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 Next Topics

• Device and technology impact

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