Sequential VHDL Statements

Dr. Yann-Hang Lee

yhlee@asu.edu
Control Flow Sequential Statements

 Sequential statements tend to look a lot like most

modern structured programming languages, and
can be used in much the same way.
 If - then - else statements
 CASE statements
 While loops
 For loops
 Next, exit statements
Conditional Control

if condition1 then
sequential statements
elsif condition2 then -- note strange spelling
sequential statements
. . .
else
sequential statements
end if;
If then else example

if memreq = '1' then

if read = '1' then
memdata <= MEM ( address );
else
MEM (address) <= memdata;
end if
end if;

(We assume here that memreq and read are type BIT, not
BOOLEAN. Note how the condition – a boolean
expression -- must be written. )
Selected Control – (CASE statements)

case selector is -- selctor must be discrete type,

-- character or bit string
when value1 => -- choices must cover all possible cases
sequential statements
when value2 | value3 =>
sequential statements
when value4 to value7 =>
sequential statements
when OTHERS =>
sequential statements
end case ;
CASE example

case X_in is
when '0' => y_out <= '1' after tph;
when '1' => y_out <= '0' after tpl;
when 'X' => y_out <= 'X' after (tph+tpl)/2;
others => y_out <= 'X' after tpl;
end case;
A Typical use of CASE: FSM

A part of a process used to model the next state computation for

a finite state machine.

case machine_state is
when sv0 => machine_state <= sv1
when sv1 => machine_state <= sv2;
when sv2 => machine_state <= sv3;
when sv3 => machine_state <= sv0;
end case;
Typical use of CASE: Multiplexer

Model the output value generation for a finite state

machine.

case Current_state is
when sv0 | sv1 | sv2 => Z_out <= '0';
when sv3 => Z_out <= '1';
end case;
While Loops

 Form:

while condition loop

sequential statements
end loop;
 Example:
while bus_req = '1' loop
wait until ad_valid_a = '1';
bus_data <= data_src;
msyn <= '1' after 50 ns;
wait until ssyn = '1';
msyn <= '0';
end loop;
Note about While Loops

In general,

 while loops have time-varying conditions

 Do not lend themselves well to synthesis.

For Loops

for index in range loop

sequential statements
end loop;

where index is an identifier NOT previously declared

and visible as an constant only within the loop
where (discrete) range defines the left and right
bounds
 enumeration (‘a’, ‘b’, …), range (1 to 127)
For Loop Example

Example: where x_in is an array of inputs

tval := ‘1’;
for i in x_in’range loop
t_val := t_val and x_in(i) ;
end loop;

-- the range of an array consists of the values of left

index, direction, and right index.
Next

 branches back to the beginning of the loop (like a Fortran

CONTINUE statement).
loop
sequential statements
next when condition
sequential statements
end loop;
Exit

 branches completely out of the loop to the first

statement following the end loop;
loop
sequential statements
exit when condition
sequential statements
end loop;
 Example: where x_in is an array of inputs
for i := 2 to x_in'length loop
new_val := new_val and x_in(i) ;
exit when new_val = '0';
end loop;
Process Termination

 Form
WAIT;

 Not normally appropriate for modeling real hardware

 With no condition to ever be satisfied, the process
will never resume.