Timing Model Reduction for

Hierarchical Timing Analysis

Shuo Zhou
Synopsys
November 7, 2006
 Outline
• Static Timing Analysis in Design Flow
• Hierarchical timing analysis
• Proposed Techniques
– Iterative timing model reduction algorithm b
ased on a biclique-star replacement techni
que.
• Experimental Results
• Conclusions
2
Static Timing Analysis in Design Flow
• Static Timer is integrated in each stage.
• Need efficient static timer.
Design Flow
Floorplaning

Synthesis Static Timing

Analysis

Placement
&Routing 3
 Hierarchical Timing Analysis
• Hierarchical timing analysis is essential for
hierarchical design.
• Consider circuits inside the blocks to be fixed.
• Complexity O(n): n is #edges in timing models.

gates
gates

gates

Partition Design Characterize Blocks 4

into Blocks into Timing Models
 Problem Statement
• Timing model minimization for
hierarchical timing analysis:
– Given a hierarchical block, construct
an abstract timing model with minimal
number of edges that covers the
longest and shortest path delays of
each pair of input and output in the
block.
5
 Previous Works
• Transform timing graph [Visweswariah ICCAD’9
9, Moon DAC’02].
– Perform serial/parallel edge merging.
• Represent delay matrix with minimal number of
edges.
– Optimal realization of a distance matrix [Haki
mi Quart. Appl. Math. 22 (1964), Chung http://
www.math.ucsd.edu/˜fan].
– Biclique-star replacement for bicliques with un
it edge delay [Feder Symp. on Theoretical As
pects of Computer Science (2003)]. 6
Terminologies: Bipartite Timing Model
• G = {B, D, E}
– Input set B, output set D, and edge set E
– Longest and shortest delays.

7
 Timing graph Bipartite timing model
2 1 1 3
1 4 9 9
7
1 1 8
2 1 2 6
2 5 7 10 2 7 10
1 1 2 4
1 6 1 8 3 11 3 5 11
3

path: 1->4->5->7->8->10
8
 Delay matrix
• Element on row i col j is delay from input i to ou
tput j,  for disconnected input i and output j.
• Row i implies input delay vector = {di,j| di,j from i
nput i.}
Bipartite timing model Delay matrix Outputs
3 O 4 O 5 O6
1 4
7 I1 3 7 8
8

Inputs
6
2 7 5 I2  6 7
4 I3   5
3 5 6
9
 Star
• Gs = (Bs, Ds, s, Es)
– Bs input set, Ds output set, center vertex s.
– Edges (i,s) and (s,j).

Star
1 4
4 1

2 3 s 3 5
1 4
3 6
10
 Biclique-Star Replacement
• Basic idea: match various input delay vectors to a
pattern and cover each input delay vector by one edge
plus the pattern.

11
Biclique #edge = 9 star #edge = 6
1 2 4 1 4
3 Replace 0 2
4
3 3 5
2 4 5 dij = dis+dsj 2 1 s
5 2 4
4 5
3 6 6 3 6
Outputs Outputs
O 4 O5 O 6 O4 O5 O6
I1 2 3 4 0+ 2 3 4 Pattern
Input =
I2 3 4 5 1+ 2 3 4
vectors
I3 4 5 6 2+ 2 3 4
12
Bipartite Timing Model Reduction

Biclique Search

Reduction Ratio Repeat

Evaluation
ratio = #edges_covered/(r+c)
Reduction > 1 Re-evaluation

Biclique-star
Replacement
13
 Delay Vector Subtraction
• Input delay vector subtraction Sub(Ia, Ib)
– Distance vector V(Ia,Ib) = {jIa,Ib =da,j – db,j| j
[1..c]}
• Input vectors Ia, Ib share a pattern if all jIa,Ib ar
e equal. O O O 4 5 6
I1 2 3 4
I2 3 4 5
Sub(I2,I1)
V (I2,I1)= 1 1 1
14
 Biclique Expansion for Replacements
• Choose an input delay vector as the pattern ve
ctor.
• Expand the biclique of the pattern vector by co
vering as many as possible input vectors.
• Replace the biclique by a star.

Biclique Expansion (G, Ia, Gc)

I. Add edges (a,j) to biclique Gc;
II. For each input vector Ii
1. Vector subtraction Sub(Ii,Ia);
2. If all jIi,Ia = 0Ii,Ia add edges (i, j) to Gc.
Biclique-star Replacement (Gc,Ia,Gs)
I. Add inputs, outputs, center vertex s, and edges (i,s), (s,j) to Gs
II. da,s = 0, ds,j = Ia,j;
III. For each edge (i,s) in Gs 15
1. di,s = 0Ii,Ia;
 #edge = 9 #edge = 8
1 2 4 1 4
3 0 I12
4
3 Replace 1 3
4 2 s 5
2 5 5 0
I2,I1
4
45 5
4
3
7 6 3 76

step 1 O4 O 5 O 6 step 2 O4 O5 O 6
I1 2 3 4 I1 2 3 4
I2 3 4 5 I3 4 5 7
Sub(I2,I1) Sub(I3,I1)
V (I2,I1) = 1 1 1 V(I3,I1) = 2 2 3
0I2,I1 16
 Don’t Care Edges
• Edge (i,j) is a don’t care edge in a biclique star replacement if pat
h delay di,s + ds,j < di,j.

Biclique Star
1 2 4
3 1 4
4 0 2
Replace 3
5 s 5
45 2 4
3 7 6 3 6
7
Don’t Care Edge
17
 Biclique Expansion with Don’t Cares

• Choice: try each  in distance vector as di,s.

• For d3,s = 
– di,j is covered if di,s + ds,j = di,j, i.e., j = .
– di,j is a don’t care edge if j > .
– Output j has to be removed if j < .

18
 O 4 O5 O6
I1 2 3 4
I3 4 5 7

V(I3,I1) = 2 2 3

1 4 1 4
0 2 0 2
3 5 s 3 5
s
4 4
2 3
3 6 3 6
#edges covered #edges covered
increases by 2 decreases by 1 19
 Biclique Expansion and Replacement with
Don’t Cares
Biclique Expansion with Don’t Cares (G, Ia, Gc)
I. Add edges (a,j) to Gc;
II. For each input vector Ii
1. Vector subtraction Sub(Ii,Ip);
2. For each j in the distance vector
For each k in distance vector
if k = j #covered++;
else if k < j #removed +=edges to output k;
3. If maximum (#covered - #removed of j )> 1;
For each k in distance vector
if k  j Add edge (i,k) to Gc;
else remove output k and edges to k.
Replacement with Don’t Cares (Gc, Ia, Gs)
I. Add inputs, outputs, center vertex s, and edges to Gs
II. da,s = 0, ds,j = Ia,j;
III. For each edge (i,s) in Gs
20
1. di,s = min( Ii,Ia ).
 #edge = 9 #edge = 7
1 2 4 1 4
3 0 2
4
3 Replace 1 s 3
4 2 5
2 5 5 2 4
45 Min I1
7 3 7 6
3 6
Don’t Care Edge
step 1 O4 O5 O6 step 2 O 4 O5 O 6
I1 2 3 4 I1 2 3 4
I2 3 4 5 I3 4 5 7
Sub(I2,I1) Sub(I3,I1)
V (I2,I1)= 1 1 1 V(I3,I1) = 2 2 3
21
 Bipartite Timing Model Reduction
Biclique Search

Reduction Ratio Star Graph to

Evaluation
ratio = #edges_covered/(r+c) Bipartite Graph
Reduction > 1 Re-evaluation

Biclique-star
Replacement 22
 Star Graph to Bipartite Graph
Transformation
bipartite graph
star timing model 1 s1
1 5 s2
2
s1
6 Split s1,s2
2 3 9
s2 7
4 8
3 Recover
8 Stars s2' 7
4 s1' 5
9 23
6
 Correctness
• G: the bipartite timing model before the reduct
ion.
• G': the timing model after the reduction.

Edge delay di,j of any connected input i and outp

ut j in G is covered by the longest path delay d
i,j' from input i to output j in G' after the reducti
on.

24
 Experimental Results
• Test cases
– Block 1: 8499 inputs, 16885 outputs, and 1
38,360 edges
– Block 2: 4260 inputs, 7728 outputs and 103
,414 edges
– EG-- #edges in original timing graph of the bl
ock.
– EB--#edges in bipartite timing model.
– Em--#edges after timing model reduction.
• Reduction rG = (EG – Em)/ EG.
• Reduction rB = (EB – Em)/ EB.
25
• |di,j – di,j’| <= Err_bound, where di,j and di,j’ are dela
ys from input i to output j before and after the redu
ction.

Block1 EG = 138,360, EB = 262,491

Err_bound
Em rG rB
(ns)
0 249,032 -80.0% 5.1%
0.1 41,696 69.9% 84.1%
1.0 36,980 73.3% 85.9%
10.0 35,981 74.0% 86.3%
100.0 36,169 73.9% 86.2%
Buffer1 delay = 1.34ns. 26
 Block2 EG = 103,414, EB= 465,190
Err_bound
Em rG rB
(ns)
0 397,384 -284.3% 14.6%
0.01 49,613 52.0% 89.3%
0.10 29,477 71.5% 93.7%
1.0 21,192 79.5% 95.4%
10.0 20,262 80.4% 95.6%
Buffer 1 delay = 0.74ns.

27
 Conclusions
• We propose a biclique-star replacement
technique and develop an iterative timing
model reduction algorithm based the
proposed technique.
• By allowing reasonable error bounds, the
experimental results show that the proposed
algorithm can effectively reduce the number
of edges in the timing model.

28
Thanks!

29
 References
• C.W. Moon, H.~Kriplani, and K.~P. Belkhale, “Timing model extraction
of hierarchical blocks by graph reduction”, in DAC’02, 152-157.
• C. Visweswariah and A.R. Conn, “Formulation of static circuit optimizat
ion with reduced size, degeneracy and redundancy by timing graph m
anipulation”, in ICCAD’99, 244-251.
• S. L. Hakimi and S. S. Yau. “Distance matrix of a graph and its realiza
bility.” Quart. Appl. Math. 22 (1964), 305–317.
• F. Chung, M. Garrett, R. Graham, and D. Shallcross. “Distance realizat
ion problems with applications to internet tomography.” http://www.mat
h.ucsd.edu/˜fan.
• T. Feder and A. Meyerson and R. Motwani and L. O' Callaghan and R.
Panigrahy, “Representing graph metrics with fewest edges.” in Proc. of
Symp. on Theoretical Aspects of Computer Science (2003), 355--366.

30