ECE-E434 Digital Electronics

Lectures 13: Memory Circuits

Instructor: Pouya Dianat

Nov 7 2017
 ECE-E434
Digital Electronics
Memory Circuits– Ch. 16

Announcement
• Midterm grades will be released on Thursday
Nov 9 2017
• HW Set # 4 is due on Tuesday Nov 14 2017
 ECE-E434
Digital Electronics
Memory Circuits– Ch. 16

Types of Digital Circuits

Digital Circuits

Combinationa
Sequential
l
 ECE-E434
Digital Electronics
Memory Circuits– Ch. 16

Combinational vs. Sequential

• Combinational Circuit:
 Output depends on the present value of inputs
 No memory
• Sequential Circuits:
 Output depends on current and previous states of inputs
 Has memory
 Requires a timing generator (clock)
 ECE-E434
Digital Electronics
Memory Circuits– Ch. 16

General Approaches to (Digital) Memory

Positive feedback
loop
Static sequential
circuits
(Latch, FF, SRAM)
Bi-stable input

Memory Circuit
Charge/Discharge
of a cap.
Dynamic sequential
circuits
(DRAM)
Requires refreshing
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Digital Electronics
Memory Circuits– Ch. 16

Latches and Flip-Flops

Latches

• Two cross-coupled inverters

• Operates based on positive feedback loop
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Digital Electronics
Memory Circuits– Ch. 16

How do latches work?

• Let’s find the possible operating points by superimposing load curves.
• Points A and C are stable solutions: The latch can remain in them indefinitely.
• Point B is unstable: The latch can not remain in it for a significant amount of time.
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Digital Electronics
Memory Circuits– Ch. 16

Latches: Why is point B unstable?

• It relies on two factors:
 Existing noise in the circuit
 Voltage gain greater than unity (in magnitude)
 Connection in positive feedback
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Digital Electronics
Memory Circuits– Ch. 16

Latches: Bistable Circuits

• When X is H, Z is L
• When X is L, Z is H
• The circuit has two complementary states
(X and Z)
• It operates in a bi-stable mode.
• The state depends on the external force
and memorizes the effect of that force.
• It can store 1 bit of information.
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Digital Electronics
Memory Circuits– Ch. 16

The case of triggered Latch, aka Flip-Flop

• A Set-Reset (SR) Flip-Flop:
 Cross coupled NOR gates
 Set mode: It is storing a logic 1; S is H and R is L.
 Reset mode: It is storing a logic 0; S is L and R is H.
 Memory/rest mode: both S and R are L.

Question: What happens if both R and S are H?

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Digital Electronics
Memory Circuits– Ch. 16

SRFF using CMOS

A Clocked Version of SR Flip-Flop

Properties
• Set and Reset may only be done when
the Clock is H.
• Only NMOS transistors do logic
• 0 static power dissipation
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Digital Electronics
Memory Circuits– Ch. 16
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Digital Electronics
Memory Circuits– Ch. 16

Part (a)
• Before regeneration happens: vQ=0V.
• The circuit is effectively a pseudo-NMOS;
• VOL of this pseudo-NMOS should be less than VDD/2 so that it can switch the next inverter.
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Digital Electronics
Memory Circuits– Ch. 16

Part (b)
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Memory Circuits– Ch. 16
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Digital Electronics
Memory Circuits– Ch. 16

SRFF using CMOS: Another Version

A Clocked Version of SR Flip-Flop
using Pass Transistor Logic

Very popular for making Static Random Access Memories (SRAM)

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Digital Electronics
Memory Circuits– Ch. 16

D Flip-Flop
• The output takes the value of the data, D, when the clock goes H;
• otherwise it is in memory state.
• It is edge-triggered.
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Digital Electronics
Memory Circuits– Ch. 16

D Flip-Flop
Implementation
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Digital Electronics
Memory Circuits– Ch. 16

D Flip-Flop: Master-Slave Configuration