CLOCK

• Activities on the system bus is synchronized by the system

clock
• Activities include:
– Reading from memory or / IO
– Writing to memory /IO
• Any read or write cycle is called a bus cycle (machine cycle)
• 8086 ,a bus cycle takes 4 T states, where one T state is
defined as the ‘period’ of the clock.
• During a machine cycle, one specific operation- reading or
writing is accomplished.
• 4 basic machine cycles
 Memory Read
 Memory Write
 I/O Read
 I/O Write
 Read Machine Cycle
Steps involved in a typical read machine cycle
• Place on the address bus ,the address of the location
whose content is to be read .Done by the processor.
• Assert the read control signal which is part of the
control bus.
• Wait until the content of the addressed location appears
on the data bus.
• Transfer the data on the data bus to the processor
• De-activate the read control signal .The read operation is
over and the address on the address bus is not relevant
anymore.
BHE/S7
 Wait Cycle
•If the access time for a device > that permitted by
the timing of 8086, extra clock cycles termed wait
states need inserted in the bus cycle .
•Applicable for reading and writing
•If the READY signal is found low at the end of T2,an extra
cycle, Tw is inserted into the bus cycle ,between T3 and T4

•All signals on the bus remain unchanged during Tw

•In the middle of Tw , READY signal is checked.

High:- next T state will be T4
Low:- another wait state will be inserted.

•Bus cycles can be lengthened to accommodate slower

devices.

•A wait state generator can be connected to the RDY pin of

clock generator to control the READY pin.
 X1 X2

8284A CLK 8
Clock READY 0
generator 8
RES
RESET 6

RDY

Wait state
generator Fig:-Insertion of wait state generator to add
wait states
 Write Machine Cycle
Steps involve in write machine cycle are:
• Place on the address bus ,the address of the
location to which data is to be written
• On the data bus, place the data to be written.
• Assert the write control signal which is part of
the control bus.
• Wait until the data is stored in the addressed
location.
• De-activate the memory write signal .This ends
the memory write operation
Simplified Write Machine Cycle

T1 T2 T3 T4
Clock

Address/Status

Address/Data

WR
 Instruction Cycle
• Time taken by processor to execute an instruction- specified in terms of
no. clock cycles needed to do it.
• Once instruction is fetched and ready to be executed, then it can be
decoded and execution can be set.
• Fetch-execute cycle can be divided into 6 stages
– Fetch instruction
– Decode instruction
– Calculate operand address
– Fetch operand
– Execute instruction
– Write/store result in memory
•The time for all these activities should constitute the instruction cycle.

•Example we fetch an ADD instruction - 2-byte instruction

* First 8-bits specify operation.
* Other bits identify the source and destination operands.

•The ADD instruction may have a memory operand or an immediate

operand.

•Depending on the way operand is specified there is a need of having

to calculate the operand address.

•The BIU will separate the operation type from the operands and fetch any
operands from memory if required, and after that execution in done.

•In the execution phase, any instruction involving loading from or storing
into memory cause a read /write cycle to occur.

•An instruction which moves data between two registers, or must execute
a more complicated instruction with operands available within the
processor, is done in the Arithmetic and Logic Unit (ALU) alone.
Instruction Fetch Cycle
•The instruction is in memory and fetching it requires a memory read cycle
which takes 4 T states .

•In 8086, ‘fetch and execute ‘are overlapped –

- instructions are fetched during the execution phase of an earlier
instruction

•Time normally required to fetch instructions "disappears", because the

Execution unit(EU) executes instructions that have already been pre-fetched by
the BIU.

•Instruction cycle time does not include the time required to fetch the
instruction .

•For instructions which have memory operands not specified directly ,there is a
time involved in calculating the ‘effective address’.

•Example:- In case of addressing modes like

based indexed mode or relative based indexed mode .The BIU takes time to do
address calculation ,and this time is also included in the instruction cycle.
No Instruction No of clock cycles
for execution
1 MOV AX, BX 2
2 ADD AX, BX 2
3 MUL BX 133
4 MOV BX, N 4
5 CMP AX, [BX][SI] 9+ EA
6 JNZ label 16/4
7 LOOP Label 17/5

Table : Execution time of sample instructions

Table:-No of cycles involved in calculating Effective Address

No. Addressing mode No. of clocks for

calculating EA
1 Direct 6
2 Register Indirect 5
3 Register relative 9
4 Based indexed with BP as base 8
register
5 Based indexed with BX as base 7
register

6 Relative Based indexed with BP as 12

base register

7 Relative Based indexed with BX as 11

base register
DELAY LOOPS
• Certain amount of time or delay is associated with the execution of an
Instruction.

•Thus instruction execution gives us a means of generating a delay .

Consider instructions below,
MOV CX, 100 4 cycles
HERE: LOOP HERE 17/5 cycles

• Total no. of clock cycles required is 4+(100*17) -12 =1692 cycles

•In a system with 12 MHz clock, clock period is .083μ Sec

- Total delay in this case .083 *1692 =140 μ Sec

•It is possible to fix the value of N so as to get a desired value of delay .

•To increase the delay, we can use the NOP (No operation ) instruction which has no
operands and no function except to execute within 3 cycles.

•The NOP instruction is usually used to reserve space in programs ,for instructions
which may needed to be added later.
• Write a program to create a delay of 1 msec.
Soln:- MOV CX,N 4
HERE:NOP 3
LOOP HERE 17/5
• Most of the delay occurs within the loop
the total cycles of delay is =[(3+17) x N]-12.
• Total delay time =1 m sec =20N x 0.083 μsecs
• For 1 msec delay ,the value of N =602 or 25AH
• This value of N is inserted into program to create a delay of 1msec
• Generating delays in this manner is called software delays
• Application
Q) Generate a square wave of frequency 1 KHz at the output port with address 78H
• Solution:
AGAIN: MOV AL,0FFH
OUT 78H,AL
CALL DELAY_1MS
MOV AL,00
OUT 78H,AL
CALL DELAY_1MS
JMP AGAIN