Low-Power Integrated

Circuit Design
Chapter 5

Parameter extraction

CMOS Analog Design Using All-Region MOSFET Modeling 1

The different definitions of threshold voltage

 Surface potential based s  2F  VC

 Qualitative: gate voltage at which significant drain
current starts to flow
 Procedural based (details next slide)
Other approaches:
 Splitting the threshold: define weak, moderate and
strong inversion VTs
 Deconstructing the threshold: surface potential
models don’t use VT as parameter!
The standard VT extraction methods

PROBLEM: missing link between extracted

threshold and surface potential value!
Current based definition of threshold 1

 MOSFET OPERATION: Drain current and its diffusion and drift

components vs. gate voltage for a MOSFET operating in the linear
region with VDS=/2=13mV.
Current based definition of threshold 2

 Sound modeling: To accurately extract VT it is essential that

the MOSFET model includes the drift and diffusion transport
mechanisms, both important near the threshold condition.

 Extraction methods based solely on the strong (SI) or weak

(WI) inversion models are inherently inaccurate since to
determine the threshold voltage (which is found between the SI
and WI regions) experimental data are extrapolated from only
one of these two operating regions.
Current based definition of threshold 3

M. A. Maher and C. A. Mead, “A physical charge-controlled model for

MOS transistors,” Advanced Research in VLSI, MIT Press
Take Idrift = Idiff to define the threshold.

kT kT
  (Cox  Cb )
QITH  nCox
q q

Cox Cb are the oxide and depletion capacitances per unit area

The carrier charge density at threshold is the

effective channel capacitance per unit area
times the thermal voltage, or the thermal
charge per unit area
Charge-based all-region MOSFET model

I D  I F  I R  I S i f  ir 
QI
qI  Normalized inversion
 t
nCox charge density

i f  r   qIS  D 2  2qIS  D  qIS  D  1  i f r   1

Drift Diffusion

At threshold q’IS = 1 if = 3 at pinch-off

7
Classical and current-based threshold definitions

Difference in VT
Inversion
Physical Meaning Surface potential relative to the
charge density
classical definition

2F  V   n  1 Cox
Surface concentration
of electrons= bulk  t 0
concentration of
holes
Drift component =
Diffusion component
 t   n 
of drain current
 n 
2F  V  t ln   nCox t 1  n ln  
 n 1    n  1 
What’s the difference with the EKV approach?

Our approach ITH = 3IS= 1.5(W/L)µC’oxnφt2

EKV ITH = 0.608ISPEC= 1.216(W/L)µC’oxnφt2

Constant current VT-extraction procedure

if=3 at pinch-off

VG  VT 0
VP 
n

VP[V]

Pinch-off voltage as a function of VG

10
 Specific current and threshold voltage
gm 2 VDS 1  i f 1
  1  i f  1  ir  ln
I D nt  1  i f  1  ir  t 1  ir  1

For VDS/t<<1 we have ifir

gm

1 VDS 1 i f  ir 1 ID / IS
 
I D nt 1  i f t 2 1  i f 1 2 1  i f 1
or

gm gm 1 t ID t
 IS   ID
ID ID max
1 i f 2VDS 1  i f 1
i f 3
2VDS

For VDS/t=1/2 and if=3, we have ISID. For VDS/t=1/2 and if=3, more accurate values for
gm/ID and IS are 0.53 times the peak value of gm/ID and 1.13 times the measured current,
respectively .

CMOS Analog Design Using All-Region MOSFET Modeling 11

Transconductance-to-current ratio of a MOSFET
vs. gate voltage for VDS  Φt/2 and VS=0.

gm dI D d ln I D
 
I D I D dVG dVG
CMOS Analog Design Using All-Region MOSFET Modeling 12
.
gm/ID VT-extraction procedure

gm 1 dI D g ms  g md 2
  
I D I D dVG nI D nt  1  i f  1  ir 
gm 1

ID VDS 0
nt 1  i f

Thus, at threshold (if =3) gm/ID

is at
½ of its maximum value,
disregarding the variation of n

Considering VDS = (1/2)kT/q,

gm/ID =0.531 (gm/ID)max
.
gch/ID VT-extractor procedure

g ch 1 dI D 2
 
ID I D dVS t  1  i f  1  ir 
g ch 1

ID VDS  0
t 1  i f

Thus, at threshold (if =3)

gch/ID is at
½ of its maximum value

Considering VDS = (1/2)kT/q,

gch/ID =0.531 (gch/ID)max
ID =0.88IS
Automatic VT-extractor circuit

 Considering VDS = (1/2)kT/q, at threshold (if =3) ,

gm/ID =0.531 (gm/ID)max and ID =0.88IS
Application 1

Extracted VT values vs. channel length for gm/ID, gch/ID and constant
current methods for NMOS transistors with channel length ranging
from 100nm to 10μm and W=120nm, in a 90nm CMOS technology.
Application 2

VT measurements using gm/ID and constant current (CC) methods

for 20 matched NMOS transistors
(W=12µm and L=0.5µm – 0.35µm CMOS process) at room temperature.
The VT average values were 629mV (gm/ID)
and 612mV (CC) and the relative standard deviation are 0.59% ( gm/ID)
and 0.54% (CC).
Application 3

CD4007 irradiated with doses up to

200Gy (x-rays of 6MV).

variation of the output voltage as function

of the total accumulated dose for PMOS transistors
from the IC CD4007.
Pinch-off voltage vs. gate voltage

VP  VS  / t  1  i f  2  ln  1 i f 1 
For if=3, the pinch-off voltage is equal to the source voltage.
CMOS Analog Design Using All-Region MOSFET Modeling 19
Slope factor n=1/(dVP/dVG) vs. gate voltage

CMOS Analog Design Using All-Region MOSFET Modeling 20

Plot of 1/(n-1)2 vs. pinch-off voltage

n  1   /(2 2F  VP )

1 4VP 8F
 2  2
( n  1) 2
 

The slope and the y-intercept of the interpolation line give =0.60 V1/2 and
2F=0.89 V
CMOS Analog Design Using All-Region MOSFET Modeling 21
 Mobility - 1
The dependence of the mobility on the transverse electric field is written as

0

 QB  QI 
1    
  s 
Problem: Determine the mobility variation for cases in which the depletion charge
is much higher than the inversion charge density

QB  QBa    Cox

  QI (n  1) / n  QBa  2F  VP

0
 with    Cox  /  s
1   VP  2F

CMOS Analog Design Using All-Region MOSFET Modeling 22

 Mobility-2

n 1
 
 t2 W / 2 L 
I S  Cox VG
+
VS VS+t/2
1   VP  2F
 t2 W / 2 L 
0Cox

Parameter VT0 2F  

Value 0.552 V 0.89 V 0.60 V1/2 8.8 A 0.75 V-1/2

CMOS Analog Design Using All-Region MOSFET Modeling 23

 Comparison between experiment and the
ACM model in a 0.35 m technology-1

Experiment and ACM model for a long-channel (L=3.2 m) NMOS transistor in a 0.35
m CMOS technology, with VS=0 and VDS= 13 mV. The maximum error for currents is
around 30% for VG = 3.3 V
CMOS Analog Design Using All-Region MOSFET Modeling 24
Comparison between experiment and the
ACM model in a 0.35 m technology-2

Plots of experimental and modeled transconductance-to-current ratio vs.

drain current
CMOS Analog Design Using All-Region MOSFET Modeling 25
Comparison between experiment and the
ACM model in a 0.35 m technology-3

Plot of the experimental and modeled current vs. gate voltage for a
minimum-length NMOS transistor in a 0.35 m technology.

CMOS Analog Design Using All-Region MOSFET Modeling 26

 The Early voltage -1
1 1 dI D 1 I D VT 1 I D L 1 1
    
VA I D dVD I D VT VD I D L VD VADIBL VACLM

VT  VT 0   VSB  VDB  1

1 I D L 1   I  YD
  D
VACLM I D L VD I D  L  VD

n  
 F   V  
ID 2
VADIBL  t  1   1 VACLM  2aL(  L   bi DB SL )
2  IS   2a  a

CMOS Analog Design Using All-Region MOSFET Modeling 27

The Early voltage -2

Experimental drain and source currents versus drain-to-source voltage for a

minimum channel length NMOS transistor (L=0.4 m) in a 0.35 m CMOS
technology.

CMOS Analog Design Using All-Region MOSFET Modeling 28

 The Early voltage -3

Derivatives of the experimental drain and source currents with respect to the drain
voltage versus drain-to-source voltage for a minimum channel length NMOS
transistor (L=0.4 m) in a 0.35 m CMOS technology.
CMOS Analog Design Using All-Region MOSFET Modeling 29
The Early voltage -4

Experimental and modeled Early voltages vs. drain-to-source voltage for a

minimum-length NMOS transistor (L=0.4 m) in a 0.35 m CMOS
technology

CMOS Analog Design Using All-Region MOSFET Modeling 30

 The Early voltage - 5

Experimental and modeled Early voltages vs. drain-to-source voltage for

transistors M1, M2, M4, and M8, for which the nominal lengths are Lmin, 2·Lmin, 4·Lmin,
8·Lmin, respectively, where Lmin=0.4 m.
CMOS Analog Design Using All-Region MOSFET Modeling 31
 The Early voltage - 6
Fitting parameters extracted for the Early voltage of NMOS transistors
in a 0.35 m CMOS technology.

Transistor  [mV/V] a [V/m2] bi  2F [V]

M1 7 2.5 1014 0.1
M2 0.8 2.5 1014 0.1
M4 0.6 2.5 1014 0.1
M8 0.45 2.5 1014 0.1

nt    FL  bi  VDB  SL

2
ID
VADIBL   1   1 VACLM  2aL(    )
2  IS   2a  a

CMOS Analog Design Using All-Region MOSFET Modeling 32

 References

 C. Galup-Montoro and M. C. Schneider, "Mosfet Modeling For Circuit

Analysis And Design", International Series on Advances in Solid State
Electronics and Technology, World Scientific, 2007
 Márcio Cherem Schneider and Carlos Galup-Montoro, "CMOS Analog
Design Using All-Region MOSFET Modeling", Cambridge University
Press, 2010
 A. Ortiz-Conde et al, “ Revisiting MOSFET threshold voltage extraction
methods”, Microelectronics Reliability, 2012
 O. F. Siebel, M. Cherem Schneider, C.Galup-Montoro," MOSFET
Threshold Voltage: Definition, extraction, and some Applications",
Microelectronics Journal, May 2012
 O. F. Siebel, M. C. Schneider and C. Galup-Montoro; "Low power and
low voltage VT extractor circuit and MOSFET radiation dosimeter“,
NEWCAS 2012, Montreal, Canada.

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