Electronics III

Integrated Circuits Layout (3)

By:
Dr. Mohamed Atef
Electrical Engineering Department
Assiut University
Assiut, Egypt
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 Others Readings and Study Materials
This PPT IS using slides based on these references

- [1] Layout of Analog CMOS Integrated Circuits, Franco Malberti.

www.ims.unipv.it/Courses/download/AIC/

- [2] The Art of Analog Layout, Alan Hasings, Prentice Hall, 2001.

- [3] IC Mask Design Essential Layout Techniques, Christopher Saint

and Judy Saint, McGraw Hill, 2002

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Noise traveling through substrate.

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Noise traveling through substrate.

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Noise traveling through substrate.

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 Noise traveling through substrate.
We have already placed guard bands around our noisy block. Now, not only
might you guard band your noisy block, but if you have a quiet block somewhere
in your circuit, you could guard band both of them. It’s like walking into
your own house as well as the band walking into theirs. Twice the isolation.

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 Noise traveling through substrate.
Here we have two floorplans of the same chip.
Our initial floorplan on the left shows the quiet stuff and the noisy stuff
placed next door to each other.
But, if you can, why not have the quiet and the noisy stuff as far away
from each other as you possibly can, as in the floorplan on the right?

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Noise traveling through substrate.

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 very noise-sensitive wires
Shielding:

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 very noise-sensitive wires
Shielding:

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 very noise-sensitive wires
Shielding:

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 very noise-sensitive wires
Shielding:

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very noise-sensitive wires

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very noise-sensitive wires

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 very noise-sensitive wires
Decoupling power rail capacitors:

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very noise-sensitive wires

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