Unit - 2

Powers of 2
Powers of 2 Decimal Equivalent Abbreviation
20 1
21 2
22 4
23 8
24 16
25 32
26 64
27 128
28 256
29 512
210 1,024 1K
211 2,048 2K
212 4,096 4K
213 8,192 8K
214 16,384 16K
215 32,768 32K
216 65,536 64K
 Arithmetic Circuits

 Binary Addition - Review

 Binary Subtraction - Review

 Unsigned binary numbers

 Sign-magnitude numbers

 2’S Complement representation

 2’S Complement arithmetic

 Arithmetic Building Blocks

 Binary Addition - Review

0+0=0

0+1=1

1+0=1

1 + 1 = 10 = 0 + Carry of 1 into next position

1 + 1 + 1 = 11 = 1 + Carry of 1 into next position

 Binary Addition - Review

4 – Bit, Nibble Addition

1101 0101 1111
+1001 +1101 +1111

8 – Bit, Byte Addition

10101010 11000101 01011111
+10011000 +11010011 +11111010
Binary Subtraction - Review

0 - 0 = 0
1 - 0 = 1
1 - 1 = 0
10 - 1 = 1
 Binary Subtraction - Review

4 – Bit, Nibble Subtraction

1101 1100 1100
-1010 -0101 -0111
0011

8 – Bit, Byte Subtraction

11001000 11010101 11011111
- 01111101 -11000011 -11001010
 Unsigned Binary Numbers
 In some digital applications all the data is either positive or
negative. For an 8-bit data, the smallest 8-bit number is
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0 =00H = 0010

And the largest is

D7 D6 D5 D4 D3 D2 D1 D0
1 1 1 1 1 1 1 1 =FFH = 25510

With 16-bit numbers the total range is;

0000 0000 0000 0000 = 0000H = 0010
1111 1111 1111 1111 = FFFFH = 6553510
 Unsigned Binary Numbers
 The numbers of these types are called as UNSIGNED BINARY
NUMBERS because all of the bits in the binary number are
used to represent the magnitude of the corresponding
decimal number.

 LIMITS: For an 8-bit system all unsigned arithmetic magnitudes

must be between 010 and 25510.

 Therefore each number being added or subtracted must be

between 010 & 25510. Also the answer must fall in the range of
010 to 25510.

 If any magnitudes are greater than 25510, you should use 16-
bit arithmetic which means operating on the lower 8-bits first,
then on the upper 8-bits.
 Unsigned Binary Numbers
OVERFLOW:
 In 8-bit arithmetic addition of two unsigned numbers whose
sum is greater than 25510 causes an Overflow, a Carry in the
9th Column.

 Most microprocessors have a logic circuit called a CARRY Flag,

this circuit detects a Carry into the 9th Column and warns the
user that the 8-bit answer is invalid.
 Signed Magnitude (Binary) Numbers
 Binary numbers can be positive or negative. In order to
represent these numbers signed numbers are used.
 For signed numbers, the MSB represents the sign of the
number and the remaining bits represent the magnitude of
the number.
 For a 4-bit system,
D3 D2 D1 D0
= + 510
Magnitude
SIGN BIT

D3 D2 D1 D0
= - 610

SIGN BIT Magnitude

 Signed Magnitude (Binary) Numbers
For a 8-bit system,
D7 D6 D5 D4 D3 D2 D1 D0
0 0 1 1 0 1 0 0 =+5210
Magnitude = 5210
SIGN BIT

D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 1 0 1 0 0 =-5210
Magnitude = 5210
SIGN BIT
 Signed Magnitude (Binary) Numbers
Range of Sign-Magnitude Numbers
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 1 =+110

D7 D6 D5 D4 D3 D2 D1 D0
0 1 1 1 1 1 1 1 =+12710
SIGN BIT
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 0 0 0 0 1 =-110

D7 D6 D5 D4 D3 D2 D1 D0
1 1 1 1 1 1 1 1 =-12710
 Signed Magnitude (Binary) Numbers
Range of Sign-Magnitude Numbers
 As long as the data is in the range of -127 to +127 you can use 8-bit
arithmetic. But if the data has magnitude greater than 127, then
you have to use 16-bit arithmetic.

 For 16-bit data, the range for negative numbers are from
1000 0000 0000 0001 (-110) to
1111 1111 1111 1111 (-32,76710)

 For 16-bit data, the range for positive numbers are from
0000 0000 0000 0001 (+110) to
0111 1111 1111 1111 (+32,76710)
The main advantage of Sign-Magnitude numbers is their
simplicity. The negative numbers are identical to positive numbers
except for the Sign bit.
 2’s Complement Representation

Introduction:

There is a rather unusual number system that leads to

the simplest logic circuits for performing arithmetic
known as the 2’s Complement representation.

This system is widely used in the microcomputer

architecture and programming.
 2’s Complement Representation
1’s Complement:
 The 1’s complement of a binary number is the number that
results when we complement its each bit.

 The following figure show how to produce the 1’s complement

with logic circuit.
X3 X2 X1 X0

X3 X2 X1 X0

 Since each bit drives an Inverter, the 4-bit output is the

1’s Complement of the 4-bit input number.
 2’s Complement Representation
1’s Complement:

X3X2X1X0 = 1000 1’s complement X3X2X1X0 = 0111

X3 X2 X1 X0

X3 X2 X1 X0

•The same principle applies to a binary numbers of any length.

•Complement each bit to obtain the 1’s Complement.

4-bit, 1010 1’s Complement = 0101,
8-bit,1110 1100 1’s Complement = 0001 0011
16-bit 0011 1111 0000 0110 1’s Complement =1100 0000 1111 1001
 2’s Complement Representation
2’s Complement:
 The 2’s complement is the binary number that results when we
add 1 to the 1’s complement.
 As a formula
2’s Complement = 1’s Complement + 1
For example, to find the 2’s Complement of 1011
1’s Complement 0100
+1 + 1
0101
Numbers 1’s Complement 2’s Complement
1110 1100 0001 0011 0001 0100
1000 0001 0111 1110 0111 1111
0011 0110 1100 1001 1100 1010
 Positive and Negative Numbers
1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111

-7 - 6 -5 -4 -3 -2 -1 0 +1 +2 +3 +4 +5 +6 +7

• Before and After are synonymous with “Negative” and “Positive”.

• The number line of basic algebra is shown above .
• “0” marks the origin, positive numbers on the right and negative
numbers are on the left.
Magnitude Positive Negative
1 0001 1111
2 0010 1110
3 0011 1101
4 0100 1100
5 0101 1011
6 0110 1010
7 0111 1001
8 - 1000
 Positive and Negative Numbers
Magnitude Positive Negative
1 0001 1111
2 0010 1110
3 0011 1101
4 0100 1100
5 0101 1011
6 0110 1010
7 0111 1001
8 - 1000
 The MSB is the Sign bit, “0” represents a +ve sign and “1” represents for a
–ve sign.
 The negative numbers are the 2’s complement of the positive numbers.
 Except for the last entry, the +ve and –ve numbers are 2’s complement of
each other.
 In other words, you can take the 2’s complement of a +ve binary number
to find the corresponding –ve number.
 Positive and Negative Numbers
Magnitude Positive Negative
1 0001 1111
2 0010 1110
3 0011 1101
4 0100 1100
5 0101 1011
6 0110 1010
7 0111 1001
8 - 1000
 +3 0011 -3 1101
 After taking the 2’s complement of 0011, we get 1101, which represents -3.
 The principle also works in reverse - 7 = 1001 +7 = 0111
 What does the foregoing mean? It means that taking the 2’s complement is
equivalent to negation, changing the sign of the number.
 It is important because it is easy to build a logic circuit that produces the 2’s
complement. Whenever this circuit takes the 2’s complement, the output is
the negative of the input.
 2’s Complement Representation Summary
In summary, here are the things to remember about 2’s complement
representation:

 Positive numbers always have a sign bit of 0, and negative numbers

always have a sign bit of 1.
 Positive numbers are stored in sign-magnitude form.

 Negative numbers are stored as 2’s complements.

 Taking the 2’s complement is equivalent to a sign change.

This key idea leads to an incredibly simple arithmetic circuit that can
add and subtract.
 2’s Complement Arithmetic
ADDITION CASE 2 Positive and
CASE 1 Both positive. smaller negative.
0101 0011 +125 0111 1101
+83
0001 0000 -68 1011 1100
+16

+83 0101 0011 125 0111 1101

+16 +0001 0000 +(-68) +1011 1100
9910 0110 00112 5710 1 0011 10012

• The computer will fetch these numbers from its memory and send
them to an adding circuit.
• The numbers are then added column by column, including the sign
bits to get result.
 2’s Complement Arithmetic
CASE 3 Positive and larger negative.
+37 0010 0101
-115 1000 1101

37 0010 0101
+(-115) +1000 1101
-7810 1011 00102

CASE 4 Both negative. Conclusion:

-43 1101 0101 In every case, 2’s complement addition works.
-78 1011 0010
In other words, as long as +ve and –ve
-43 1101 0101 numbers are expressed in 2’s complement
+(-78) +1011 0010 representation, an adding circuit will
-121 1 1000 0111 automatically produce the correct.
10 2
 2’s Complement Arithmetic
Subtraction
The format for subtraction is
Minuend
- Subtrahend
Difference
CASE 1 Both positive.
+83 0101 0011
+16 0001 0000
To subtract +16 from +83, the computer will send +16 to a 2’s
complement circuit to produce 1111 0000. Then it will add +83
and -16 as follows:
83 0101 0011
+(-16) +1111 0000
6710 1 0100 00112 = 0100 00112
 2’s Complement Arithmetic
Subtraction
CASE 2 Positive and smaller negative.
Suppose that the minuend is +68 and the subtrahend is -27
+68 0100 0100
-27 1110 0101

The computer sends -27 to a 2’s complement circuit to produce

+27 = 0001 1011

Then it will add +68 and +27 as follows:

68 0100 0100
+(+27) +0001 1011
9510 0101 11112
 2’s Complement Arithmetic
Subtraction
CASE 3 Positive and larger negative.
Lets use a minuend of +14 and a subtrahend is -108
+14 = 0000 1110
-108 = 1001 0100
The computer produces the 2’s complement of -108 i.e.
+108 = 0110 1100
Then it adds the numbers like this:

14 0000 1110
+(+108) +0110 1100
12210 0111 10102
 2’s Complement Arithmetic
Subtraction
CASE 4 Both are negative.
Assume that the numbers are -43 and -78.
In 2’s complement representation the numbers are:
- 43 = 1101 0101
-78 = 1011 0010
First, take the 2’s complement of -78 to get
+78 = 0100 1110
Then add to obtain
-43 1101 0101
+(+78) +0100 1110
3510 1 0010 00112 = 0010 00112
 Arithmetic Building Blocks
The basic building blocks which performs the arithmetic functions
are the Half-Adder, the Full-Adder, the Controlled Inverter.

Half Adder:
• When we add two binary numbers, we start with the Least
Significant Column.
• This means that we have to add two bits with the possibility of a
Carry. The circuit used for this is called as the Half – Adder.
• The output of the Ex-OR gate is a called as the SUM and the
output of the AND gate is called as the CARRY.
 Arithmetic Building Blocks

A B SUM CARRY

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

S  A.B A.B A  B A SUM

HALF ADDER
B CARRY
C=A.B
 Arithmetic Building Blocks
Full -Adder
 For addition of higher order columns, we have to use a Full –
Adder, a logic circuit that can add 3-bits at a time.

 The third bit is the Carry, from a lower column. This implies that
we need a logic circuit with 3 inputs and 2 outputs.

 A Full Adder consists of two Half – Adders and a OR Gate.

 Arithmetic Building Blocks
Full Adder = 2 Half Adders

Manipulating the Equations:

S=(XY)Z
C = XY + XZ + YZ = XY + Z(X  Y )

Think of Z
as a
CARRY-IN
 Arithmetic Building Blocks
Full -Adder

A SUM
B Cin A B SUM CO
FULL ADDER
CO 0 0 0 0 0
Cin
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
S=(AB)C
C = A.B + (A  B). C
 Arithmetic Building Blocks
Controlled Inverter

The above figure shows a circuit of a Controlled Inverter.

INV LOGIC

0 A7-A0 0110 1110

0 Y7-Y0 0110 1110
1 Y7-Y0 1001 0001
 Arithmetic Building Blocks
Controlled Inverter

INV LOGIC
0 A7-A0 0110 1110
0 Y7-Y0 0110 1110
1 Y7-Y0 1001 0001
• When INVERT pin is low, it transmits the 8-bit inputs to the outputs.

• When the INVERT pin is high, it transmits the 1’s complement to the
outputs.

• The Controlled Inverter is important, because during a subtraction, we

first need to take the 2’s complement of the subtrahend. Then we add
the complemented subtrahend to obtain the answer.

• With a Controlled Inverter we can produce the 1’s complement.

 The Adder - Subtractor
 In order to Add or Subtract binary numbers, we can connect Full
Adders as shown below.
 A 4 – bit, ADDER-SUBTRACTOR is shown below.
 The C0(CARRY-OUT)from each FA(FULL ADDER) is the Cin(CARRY-IN)
to the next higher FA.
 The numbers being processed are A3 – A0 and B3 – B0 and the result
being S3 – S0, with C3 being the Final CARRY-OUT.
ADDITION
A 3 A2 A 1 A 0
+ B 3 B2 B1 B0
S 3 S2 S1 S0
 The Adder - Subtractor
 During an addition, the SUB is kept at the LOW State therefore the
binary numbers B3 – B0 passes through the Controlled Inverter with
no changes. The FA’s (FULL ADDERS) then produce the correct output
SUM.
 They do this by adding the bits in each column, passing Carry’s to the
next higher column and so on.

ADDITION
A 3 A2 A 1 A 0
+ B 3 B2 B1 B0
S 3 S2 S1 S0
 8 – bit Adder - Subtractor
 An 4-bit ADDER-SUBRACTOR circuit can be extended to 8 bits by
adding the Final CARRY-OUT of the 4 bit ADDER-SUBTRACTOR circuit
as CARRY-IN to the next FA as shown below.

SUB

ADDITION
A7 A6 A5 A4 A3 A2 A1 A0
+B7 B6 B5 B4 B3 B2 B1 B0
S7 S6 S 5 S4 S3 S2 S1 S0
 8 – bit Adder - Subtractor
 During Addition SUB is kept at the LOW State.
 Starting at the LSB, the FA adds A0 & B0 and SUB. This produces a
SUM of S0, and a CARRY-OUT to the next higher FULL ADDER.
 The next higher FULL ADDER then adds A1 & B1 and the CARRY-IN to
produce S1 and a CARRY-OUT.
 A similar addition occurs for each of the remaining FULL ADDERS,
and the correct SUM appears at the output lines.

SUB
 8 – bit Adder - Subtractor
A7 A6 A5 A4 A3 A2 A1 A0 = 0111 1101
B7 B6 B5 B4 B3 B2 B1 B0 = 1011 1101
During addition SUB = 0, hence the CARRY-IN to the first column is “0”
+0 SUB
0111 1101 Hence the first FA performs the addition 0+1+1
+ 1011 1101 resulting “0” with a CARRY of 1.

The CARRY-OUT of the first FA is the CARRY-IN to the Second FA

+1 CARRY
0111 1101 In the Second Column, 1+0+0 = 1 SUB

+ 1011 1101 with a CARRY of 0 . This CARRY goes to

0 the 3rd FA
 8 – bit Adder - Subtractor
In a similar way, the remaining FA’s add their 3-input bits until we
arrive at the last FULL ADDER.
1 CARRY
0111 1101 When the CARRY-IN to the MSB appears, the
+ 1011 1101 FA produces 1+0+1 = 0 with a CARRY of 1.
011 1010
1 0011 1010 the addition process ends with a Final CARRY

SUB
 8 – bit Adder - Subtractor
Subtraction:
 During a subtraction, the SUB input is kept in the HIGH State, hence
the Controlled Inverter produces the 1’s Complement of B7 – B0.
 Furthermore, because the SUB input is the CARRY-IN to the first FA,
the circuit produces the data like this:
A7 A6 A5 A4 A3 A2 A1 A 0
- - - - - - - -
+ B7 B6 B5 B4 B3 B2 B1 B0 +1
S 7 S6 S5 S4 S3 S2 S1 S 0

SUB
 8 – bit Adder - Subtractor
A7 A6 A5 A4 A3 A2 A1 A 0
- - - - - - - -
+ B7 B6 B5 B4 B3 B2 B1 B0 +1
S 7 S6 S5 S4 S3 S2 S1 S 0
 When A7 - A0 = 0 the circuit produces the 2’s Complement of B7 - B0,
because 1 is being added to the 1’s Complement of B7 - B0.
 And when A7 - A0 does not equal to zero the effect is equivalent to
adding A7 - A0 and the 2’s complement of B7 - B0

SUB
 8 – bit Adder - Subtractor
A7 A6 A5 A4 A3 A2 A1 A0 +1 SUB
- - - - - - - - 0101 0010
+ B7 B6 B5 B4 B3 B2 B1 B0 +1
+ 1110 1110
S7 S6 S5 S4 S3 S2 S1 S0
1 0100 0001 = +65
 Example: +17 is subtracted from +82.
+82 = A7 - A0 = 0101 0010 and +17 = B7 - B0 = 0001 0001
 The Controlled Inverter produces the 1’s Complement of B7 - B0, which
is 1110 1110. As SUB = 1, the circuit performs the addition as shown

SUB
 8 – bit Adder – Subtractor with TTL Circuits
 IC 7483 is a TTL circuit with 4, FULL ADDERS.
 This means that it can add four bits (NIBBLES) at one time.

7483
 8 – bit Adder – Subtractor with TTL Circuits
 To add BYTES, we need to use two 7483s.
 The CARRY-OUT of the Lower 7483 is used as the CARRY-IN to the
Upper 7483. This allows the two 7483’s to add 8-bit numbers.
 The two 7486 IC’s form the Controlled Inverter needed for Subtraction.

7483 7483