Cross Coverage

▪ Coverage points measures occurrences of individual

values
▪ Cross coverage measures occurrences of combination
of values
▪ Interesting because design complexity is in combination
of events and that is what we need to make sure is
exercised well
▪ Did I inject all combination of request types while
my design’s FSM is in all states?

12/25/201
System Verilog Assertions And Coverage 1
7
 Cross Coverage

▪ Cross coverage is specified between two or more

coverpoints in a covergroup
▪ A cross of “N” coverpoints can be defined as the coverage
of all combinations of all the bins associated with all of the
“N” coverpoints
▪ For e.g. A cross of two coverpoints of two 4 bit signals will
cover 256 combinations as each individual coverpoint will
cover 16 combinations

12/25/201
System Verilog Assertions And Coverage 2
7
 Cross Coverage

▪ Cross coverage is allowed only between coverage points

defined within the same coverage group
▪ Cross coverage between expressions previously
defined as coverage points is also allowed

12/25/201
System Verilog Assertions And Coverage 3
7
 Cross Coverage

▪ How many combinations does this cross create?

▪ A creates -> 10 bins

▪ b_var will create 16 bins automatically
▪ Hence CC will create 160 combinations
12/25/201
System Verilog Assertions And Coverage 4
7
Cross Coverage – bins select
expression

▪ Manipulating or creating user-defined bins for cross

coverage can be achieved using bins select-
expressions.
▪ Two expressions on bins
▪ binsof
▪ intersect

12/25/201
System Verilog Assertions And Coverage 5
7
 “bins of” and intersect

▪ The binsof construct yields the bins of its expression in

arguments eg: binsof (X)
▪ The resulting bins can be further selected by including (or
excluding) only the bins whose associated values
intersect a desired set of values.
▪ binsof( x ) intersect { y }
▪ denotes the bins of coverage point x whose values
intersect the range given
▪ ! binsof( x ) intersect { y }
▪ denotes the bins of coverage point x whose values do
not intersect the range given by y.
System Verilog Assertions And Coverage
12/25/201
7
6
 “bins of” and intersect

▪ The bins selected can be combined with other selected

bins using the logical operators && and ||

12/25/201
System Verilog Assertions And Coverage 7
7
“binsof” - Examples

Default Cross – gives 16 bins

C1 - <a1,b1>, <a1,b2>, <a1,b3>, <a1,b4>
C2 - <a2, b1>, <a2,b2>, <a2,b3>, a2,b4>,
<a1,b2>, <a3,b2>, and <a4,b2>
C3 - <a1,b4>

Question: How may cross products

would be there for following?
bins c1 = !binsof(b) intersect {[100:200]};

12/25/201
System Verilog Assertions And Coverage 8
7
 Excluding cross products

▪ A group of bins can be excluded from coverage by specifying

a select expression using ignore_bins.

▪ All cross products that satisfy the select expression are

excluded from coverage.
▪ Ignored cross products are excluded even if they are included
in other cross-coverage bins of the enclosing cross.
12/25/201
System Verilog Assertions And Coverage 9
7
 Specifying Illegal cross products

▪ A group of bins can be marked as illegal by specifying a

select expression using illegal_bins.

12/25/201
System Verilog Assertions And Coverage 10
7