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BATCH NUMBER B01
SUB DOMAIN
LOW POWER AND AREA EFFICIENT
CARRY SELECT ADDDER
CONTENTS
ABSTRACT
INTRODUCTION
EXISTING SYSTEM
PROBLEM IN EXISTING SYSTEM
SOLUTION OF THE PROBLEM
SIMULATION
ADVANTAGES&APPLICATIONS
C0NCLUSION
ABSTRACT
Carry select adder is one of the fastest adders used in many data
processing processors to perform fast arithmetic function.
By gate level modification of CSLA architecture we can reduce area
and power.
Based on this modification 16-bit squareroot csla (SQRT CSLA)
architecture been devoleped.
The proposed design has reduced area and power as compared with
regular SQRT CSLA.
This work evaluates the performance of the proposed designs in
terms of area,power by hand with logical effort and through Xilinx ISE
14 .2 (VERILOG HDL) and this will be implemented in FPGA.
INTRODUCTION
Adding two n-bit numbers with a carry-select adder is done with two
adders (therefore two RCA).
The number of full adder cells are more thereby power consumption
of the design also increases
Number of full adder cell doubles the area of the design also
increased.
SOLUTION OF THE PROBLEM
The only solution of the problem present in the carry select adder
(CSLA) is the parallel ripple carry adder(RCA) with Binary-Excess 1
converter(BEC)
SIMULATION
The tools used for simulation are
PROGRAMMING LANGUAGE :VERILOG HDL
TOOL: Xilinx ISE(10.2)
APPLICATIONS
Arithmetic and logic units.
Less area(LESSCOMPLEXITY).