Semiconductor Manufacturing

Processes

Micro Electronics Fabrication

 Index
Overview
Relevance, compare with traditional ChemE process
Opportunities
Course Overview
Goal, what is expected of you
Quiz, assignment etc
Scope
Outline of the course, what is covered, what is not
References
Introduction
 Overview
Relevance:
Used everywhere
Fairly expensive (computers) to very cheap (watch)
How is it similar to / different from traditional ChemE
process?
Basic Principles are same
Level of control needed is very high
Individual features are small, but volume is high
Need to be aware of electrical properties/behavior
Developing field (processes not always mature)
Short cycle time
Not prevalent in India ==> lower exposure
 Overview
Job opportunities:
Semiconductor Complex Limited (SCL) in Chandigarh
DRDO/ISRO, BEL
Research Abroad:
Very Active research, funded by industry and government
Job opportunities, among the best for Chemical Engineers
 Course Overview
Goal: Familiarize with key processes in the chip manufacturing

ChemE

Electronics Physics

Chip
Material Science Manufacturing Economics

10000 ft view
Focus on the processes
Learn / Revise EE, optics, Material Science
Touch of economics
Few analytical techniques routinely used in semiconductor industry
 Course Overview
Need:
Memorize (substitute for experience gained by operating
the tools yourself)
Follow in journals and internet, to keep up to date
(Information is new and the text books are not up to date in
many aspects).

Quiz: 2*15 = 30
End Sem: 40
Project: 30
PROJECT WILL BE EVALUATED ONCE IN THE MIDDLE OF THE PROJECT. AND
THEN AT THE END.
 Index
Overview
Relevance, compare with traditional ChemE process
Opportunities
Course Overview
Goal, what is expected of you
Quiz, assignment etc
Scope
Outline of the course, what is covered, what is not
References
Introduction
 Chip manufacturing: Snap shot

Electrical Chip Physical Blue Print-

Design Layout Design Photo
negative

R C

Testing Creating the chip Print

Quality Control
 Scope
Types of chips

Silicon Based GaAs and others

CMOS BiPolar

Focus: CMOS (Complementary Metal Oxide Semiconductor) processes

eg chips in computer processors, cell phone etc.
Most of the chips manufactured are CMOS chips
What will / will not be covered (and
to what extent)
Electrical Design - None
Semiconductor Device Physics
VLSI (IC Design)
Device Modeling
Physical Layout Design - Absolute Minimal
Creating the chip - Main focus
Testing - Minimal

Electrical & Layout Design, Testing: Typically covered in EE courses

What will / will not be covered (and to
what extent)
Economics: Yield Issues - Minimal
Environmental Issues - Minimal
Manufacturing of microelectronics related materials like
Computer Hard Disk, CDs etc will not be covered
Processes not yet used (Next generation processes like Atomic Layer
Deposition or ALD) - Minimal

Supporting Techniques used in industry: - as necessary

 References
References:
Class Notes
Introduction to Micro Electronic Fabrication. Vol 5, Richard Jager,
2001
Micro electronic Fabrication: A practical guide to
semiconductor processing, Peter Van Zant
ULSI design by Chang & Sze
Science and Engg of micro electronic fabrication by Stephan A
Campbell
INTERNET:
www. semiconductor.net
www. eedesign.com (mostly design related though)
www.intel.com/research/silicon/
....
 Index
Overview
Relevance, compare with traditional ChemE process
Opportunities
Course Overview
Goal, what is expected of you
Quiz, assignment etc
Scope
Outline of the course, what is covered, what is not
References
Introduction
 INTRODUCTION
Chips are made on silicon wafers
Wafers look similar to the CD. Currently 8 wafers are
used and some manufacturers use 12 wafers
12 wafer Intel
CD is about 4, for comparison

IITM- EE dept has 4 wafer processing

Larger wafers have to be thicker
Less area is wasted in larger wafers
Uniformity is more difficult to achieve in larger wafers
 INTRODUCTION
In one 8 silicon wafer, 500 chips may be made
Rectangular chips

330 million transistors

in a RAM chip
Intel

Wafers are processed in a batch of 25 (called LOT)

Single wafer, batch, continuous processes
 Schematic
Zoom (Exaggerated)

Chip is formed only on the top layer of the wafer

Mechanical strength

Processes: Shape definition, Material Modification,

Deposition, Removal
 Process Classification
Back End of the Line
BEOL
Creating the devices
Connecting the
(transistors,
devices (wiring)
capacitors, resistors)

Front End of the Line

FEOL
Metal

Device 1 Device 2 Device 3 Device 4 Packaging

Silicon Wafer

Based on process sequence

 General Process Grouping
Need to make many wires (or other structures)
in many layers (view in 3D)
with different materials (conductor, insulator, semiconductor)
of small sizes ( 90 nm is the state of the art production)

Cu

Silicon di Oxide
 General Processes Grouping
Strategy

For each layer, create a carefully made photo negative

Define shape

Remove material 1 (oxide)

Add material 2 (copper)

Remove excess of 2 (copper)

Shape Definition, Deposition, Removal

In some cases, instead of deposition, Silicon di Oxide

Oxidation of silicon
 Process Classification
Unit Operations
Called Modules in Semiconductor Industry
eg. Distillation, adsorption... are unit operations
Chemical Vapor Deposition (CVD), Etch.... are the typical
unit operations (Modules) in the chip industry
Relevant Modules
Photo Lithography, CVD, PVD, Etch, CMP, Oxidation...
FEOL: Ion Implantation, Diffusion
BEOL: Electrochemical Dep
Based on process type
 Course Outline
No.
Section Focus Area
Classes
1 Introduction 1
2 BEOL 2
3 Litho , layout, design 4
4 Dep (PVD, CVD, Electro) 4
5 Removal ( Wet,dry etch, CMP) 4
6 FEOL 5 Quiz 1
7 Ion implanation, Diffusion, oxidation 5
8 Test (E Test, Binning) 3
9 Yield (KLA, Poisson Model etc) 3
10 Integration (Cu vs Al, Low K vs Oxide) 2 Quiz 2
11 Relevant Tools and techniques:AFM, SEM, FA 5
12 Process Control 2
13 Guest lectures 2

May change...
About 3 weeks for BEOL, 3 weeks for FEOL
 General Information
Complete chip production (IDM)
Electrical Design - Some companies in India (Fabless)
Physical Layout - Need interaction with Fab
Chip production - Not much in India (Fab/Foundry)
Testing - either at the customer site or at the production site
Chip production
Needs huge investment & state of the art tools
Work force
Discipline, for mass production (1 lot == 1 Million USD ==
80 kg gold)
 General Information
Chip production in India
Semiconductor Complex Limited (SCL), Chandigarh
DRDO,ISRO may have their own facilities
BEL???
0.8 m, Aluminum, 2 metal layers
International Tech Node

SCL
Minimum Feature Size (um)

0.1
Smaller node earlier means
more advanced technology
0.01
90

92

94

96

98

00

02

04
19

19

19

19

19

20

20

20

Year
 General Information
Processor Chips
Process variations
Chip Speed variations
Same design, production line, wafer --> Different chips
Memory chips
Repetitive design
Easier production --> lower cost
 Processes
Visualize the Final Product
Focus on
The parts that need to be made
The processes (for each of the part)
Finally,Focus on integrating the processes
 Chip Xsection- Simplified
Schematic
Wiring Metal connectors

Insulator

? ?

Device 1 Device 2 Device 3 Device 4

Silicon Wafer
 Chip - Simplified Schematic

Device 1 Device 2 Device 3 Device 4

Silicon Wafer

What if you want to connect Device 3 to another device 5 just at

the back of Device 3?
 Chip - Simplified Schematic
Level 2

Level 1

Device 1 Device 2 Device 3 Device 4

Silicon Wafer

Many layers of metal are necessary for current Chips (typically

4 to 5)
eg Next generation intel chips (90nm) are expected to have 7 or
8 metal layers
 Intel 7 metal SEM (90 nm node)

CDO - carbon doped oxide

Intel M1 - Metal level 1, M2 - metal level 2, etc
 IBM, multi level copper wiring
Notice: The oxide
has been removed by
etching (perhaps
with HF or KOH)
and copper is not

Also notice that the real

wiring is much more
complicated than what
we saw in the simple
schematics before

IBM
 FEOL Processes
Shape Definition
Photo Lithography
Modification
Ion Implantation
Diffusion
Rapid Thermal Anneal (RTA)
Oxidation
Deposition
Chemical Vapor Deposition (CVD)
Physical Vapor Deposition (PVD)
Removal
Chemical Mechanical Polishing (CMP)
Etching
 BEOL Processes
Shape Definition
Photo Lithography
Modification
Anneal
Deposition
Chemical Vapor Deposition (CVD)
Physical Vapor Deposition (PVD)
Electrochemical Deposition
Removal
Chemical Mechanical Polishing (CMP)
Etching
Appendix
 Acronyms
CMP - Chemical Mechanical Polishing
CVD - Chemical Vapor Deposition
PVD - Physical Vapor Deposition
SEM - Secondary Electron Microscopy
EDX - Energy Dispersion X-Ray Analysis
TEM - Transmission Electron Microscopy
 Acronyms
IC - Integrated Circuits
ASIC - application specific integrated circuit
GaAs - Gallium Arsenide device
FEOL - Front End of the line (processes up to making the device)
BEOL - Back end of the line (processes involved in creating the
wiring connections between the devices)
 Acronyms
CMOS Complementary metal oxide semiconductors
VLSI -Very large scale integration (creating one chip with many
millions of devices)
ULSI - Ultra large scale integration ( billion devices)
ALD - Atomic Layer Deposition (Depositing one layer of atoms in a
controlled manner)
MBE - Molecular Beam Epitaxy (Targetted layer by layer growth of
material)