Input-Output Organization

Megha Chaudhary
 Input-Output Interface
Input-Output interface provides a method for
transferring information between internal
storage and external I/O devices.

The purpose of communication link between the

peripheral devices and CPU is to resolve the
differences that exist between them.
 Input-Output Interface
The differences with CPU :
Peripherals are often electromechanical devices whose manner of
operation is different. A conversion of signal values may be
required.

The data transfer rate is different from the clock rate of the
CPU(usually slower). A synchronization mechanism may be
needed.

Data codes and formats in peripherals differ from the word format
in the CPU and Memory.

The operating modes of peripherals are different from each other

Each peripherals must be controlled so as not to disturb the
operation of other peripherals connected to the CPU.
 Input-Output Interface
Interface
Special hardware components between the CPU and
peripherals.
Supervise and Synchronize all input and output
transfers.
Main functions of input-output interface :
Data Conversion
Synchronization
Device selection
 I/O BUS AND INTERFACE MODULES
A typical communication structure between the
CPU and several peripherals.
 I/O BUS AND INTERFACE MODULES
Each interface decodes the address and control
received from the I/O bus, interprets them for
peripheral and provides signal for peripheral
controller.
Each peripheral has its own controller that
operates a particular device.
Each interface attached to the I/O bus contains
address decoders that monitor the address lines.
 I/O BUS AND INTERFACE MODULES
I/O Command
The processor provides a function code in the control
lines.
The interface selected responds to the function code
and proceed to execute it.
The function code is referred to as I/O command.
I/O BUS AND INTERFACE MODULES
Control Command : issued to activate the
peripheral device and inform what to do.
Status Command : used to test various status
conditions in the interface and the peripheral.
Data Output Command : causes the interface to
respond by transferring data from bus into one of its
register.
Data Input Command : interface receives an item of
data from the peripheral and places in its buffer
register.
 I/O BUS VERSUS MEMORY BUS
Computer buses can be used to communicate with
memory and I/O.
Use two separate buses, one for memory and the
other for I/O.
Use one common bus for both memory and I/O but
have separate control lines for each Isolated I/O
Use one common bus for memory and I/O with
common control lines. Memory Mapped I/O
EXAMPLE OF AN I/O INTERFACE
 ASYNCHRONOUS DATA TRANSFER
Synchronous Data Transfer
All data transfers occur simultaneously during the
occurrence of a clock pulse
Registers in the interface share a common clock with
CPU registers
Asynchronous Data Transfer
Internal timing in each unit (CPU and Interface) is
independent.
Each unit uses its own private clock for internal
registers.
 ASYNCHRONOUS DATA TRANSFER
Methods to achieve asynchronous data transfer
Strobe
Handshaking
Strobe : Control signal to indicate the time at
which data is being transmitted.
Source Initiated Strobe
Destination Initiated Strobe
 STROBE
Source Initiated Strobe
Data bus
Source Destination
unit Strobe unit

(a) Block diagram

Valid data
Data

Strobe
(b) Timing diagram
 STROBE
Destination Initiated Strobe
Data bus
Source Destination
unit Strobe unit

(a) Block diagram

Valid data
Data

Strobe
(b) Timing diagram
 HANDSHAKING
Disadvantages of strobe method
Source unit that initiate the transfer has no way of knowing
whether the destination unit has actually received the data
item.
Similarly destination unit has no way of knowing whether the
source unit has actually placed the data on the bus.
Handshake mechanism solves this problem by introducing a
second control signal that provides a reply to the unit that
initiates transfer.
Handshaking : Agreement between two independent units.
Source-initiated handshake
Destination-initiated handshake
 SOURCE INITIATED HANDSHAKE
Handshaking signals are used to synchronise
bus activities.

The two handshaking lines are data valid,

which is generated by the source unit and
data accepted generated by destination unit.
SOURCE INITIATED HANDSHAKE
 DESTINATION INITIATED HANDSHAKE
In this case the name of signal generated by the
destination unit is ready for data.

The source unit does not place the data on the

bus until it receives the ready data signal from
the destination unit.
DESTINATION INITIATED HANDSHAKE

* If one unit is faulty, data transfer will not be completed

Can be detected by means of a timeout mechanism which produces an alarm if the
data transfer is not completed within a predetermined time interval
 ASYNCHRONOUS SERIAL TRANSFER
The data transfer between two units may be serial or
parallel.
Synchronous transmission
The two unit share a common clock frequency.
Bits are transmitted continuously at the rate dictated by the
clock pulses.
Asynchronous transmission
Special bits are inserted at both ends of the character code.
Each character consists of three parts :
start bit : always 0, indicate the beginning of a character
character bits : data
stop bit : always 1
 ASYNCHRONOUS SERIAL TRANSFER
Asynchronous transmission rules
When a character is not being sent, the line is kept in the 1-
state.
The initiation of a character transmission is detected from the
start bit, which is always 0.
The character bits always follow the start bit.
After the last bit of the character is transmitted, a stop bit is
detected when the line returns to the 1-state for at least one
bit time.

1 1 0 0 0 1 0 1

Start Stop
Character bits
bit bit
 ASYNCHRONOUS SERIAL TRANSFER
Baud Rate : Data transfer rate in bits per second.
10 character per second with 11 bit format = 110 bit
per second.
Such circuit is called universal asynchronous receiver
transmitter(UART).
ASYNCHRONOUS SERIAL TRANSFER
ASYNCHRONOUS SERIAL TRANSFER
 ASYNCHRONOUS SERIAL TRANSFER
Double Buffered
New character can be loaded as soon as the previous one
starts transmission.
Possible errors
parity error : Even parity or odd parity.
Framing error : right number of stop bits are not detected at
the end of the received character.
Overrun error : CPU does not read the character from the
receiver register before the next one is available.
 MODES OF TRANSFER
Data transfer to and from peripherals may be
handled in one of three possible modes.
Programmed I/O
Interrupt-initiated I/O
Direct memory access(DMA)
 PROGRAMMED I/O
Each data transfer is initiated by an instruction in
the program.
CPU stays in the program loop until I/O indicates
it is ready for data transfer.
It is time consuming process since it keeps the
processor busy needlessly.
 PROGRAMMED I/O

Data bus Interface I/O bus

Address bus Data register

Data valid I/O

CPU
I/O read device

Status
I/O write F
register Data accepted

F = Flag bit

Data transfer from I/O device to CPU

PROGRAMMED I/O
Read status register

Check flag bit

= 0
Flag

= 1

Read data register

Transfer data to memory

Operation no
complete ?

yes

Continue
with
program
 INTERRUPT INITIATED I/O
In this type of I/O, computer does not check the
flag continuously.
Whenever any device wants attention, it sends
the interrupt signal to the CPU.
CPU then deviates from what it is doing, store
the return address from PC and branch to the
address of the subroutine.
 INTERRUPT INITIATED I/O
There are two ways of choosing the branch
address.
Vectored interrupts : The source that interrupts the
CPU provides the branch information(interrupt
vector).
Non vectored interrupts : Branch address is assigned
to fixed address in the memory.
 PRIORITY INTERRUPT
There are number of devices attached to the
computer.
They are all capable of generating an interrupt.
When the interrupt is generated for more than
one device, priority interrupt system is used to
determine which device is to be serviced first.
Devices with high speed transfer are given higher
priority.
 PRIORITY INTERRUPT
Establishing the priority can be done in two
ways:
Using Software
Using Hardware
A polling procedure is used to identify high
priority in software means.
 POLLING PROCEDURE
There is a common branch address for all interrupts.

Branch address contains the code that polls the interrupt

sources in sequence. The highest priority is tested first.

The particular service routine of the highest priority

device is served.

The disadvantage is that time required to poll them can

exceed the time to serve them in large number of I/O
devices.
 PRIORITY INTERRUPT USING
HARDWARE
Hardware priority system function as an overall manager.

It accept interrupt request and determine the priorities.

To speed up the operation each device has its own

interrupt vector.

No polling is required, all decisions are established by

hardware priority interrupt unit.

It can be established by serial or parallel connection of

interrupt lines.
SERIAL DAISY-CHAINING PRIORITY
 SERIAL DAISY-CHAINING PRIORITY
Device with highest priority is placed first.

Device sends the interrupt request the CPU.

CPU sends INTACK signal which is applied to PI(Priority in)

of the first device.

If it had requested the interrupt, it places its VAD(vector

address) on the bus. And it blocks the signal by placing 0
in PO.

The device whose PI is 1 and PO is 0 is device that sent the

interrupt request.
SERIAL DAISY-CHAINING PRIORITY

No interrupt request
Invalid : interrupt request, but no acknowledge
No interrupt request : Pass to other device (other
device requested interrupt )
Interrupt request
 PARALLEL PRIORITY INTERRUPT
It consist of the interrupt register whose bits are set
separately by interrupting devices.

Priority is established according to the position of

the bits in the register.

Mask register is used to provide facility for the

higher priority devices interrupt when lower priority
device is being serviced or disable all lower priority
devices when higher is being served.
 PARALLEL PRIORITY INTERRUPT Interrupt
register
Interrupt Enable F/F (IEN) : VAD
to CPU
set or cleared by the program disk 0
I0
y
x
Printer 1
Interrupt Status F/F (IST) : set I1
Priority 0
encoder
or cleared by the encoder Reade 2
0
I2
output r 0
0
Keyboard 3
I3
0
0
Interrupt Register:
-Each bit is associated with an Enable
Interrupt Request from IEN IST

different Interrupt Source -

different priority level
-Each bit can be cleared by a 0
program instruction. Interrupt
1 to CPU
Mask Register:
- Mask Register is associated 2 INTACK
with Interrupt Register from CPU
- Each bit can be set or cleared 3
by an Instruction
Mask
register
 INTERRUPT PRIORITY ENCODER
Determines the highest priority interrupt
when more than one interrupts take place.
Priority Encoder Truth table
 INTERRUPT CYCLE
At the end of each Instruction cycle
CPU checks IEN and IST
If IEN IST = 1, CPU -> Interrupt Cycle

SP SP - 1 Decrement stack pointer

M[SP] PC Push PC into stack
INTACK 1 Enable interrupt acknowledge
PC VAD Transfer vector address to PC
IEN 0 Disable further interrupts
Go To Fetch to execute the first instruction
in the interrupt service routine
 Direct Memory Access
In DMA there is a direct communication between
memory and peripheral devices.
CPU is idle and has no control over the memory buses.
DMA controller uses buses and transfer the data
directly between I/O devices and memory.

DBUS Address bus

BR BR High-impedance
Bus request ABUS Data bus
DMA (disable)
CPU when BG is
Controller
RD Read enabled
BG BG
Bus grant WR Write
 Direct Memory Access
BR(Bus Request) signal is used by DMA controller
to request CPU for buses.
CPU then places the bus on high impedance state
which behaves like open circuit.
CPU generates BG(Bus Grant) signal to
acknowledge BR signal.
DMA now have full control over the buses and
perform the transfer.
 DMA Transfer Modes
Transfer can be performed in two ways:
Burst transfer
Cycle stealing transfer
In burst transfer, a number of memory words are
transferred in continuous burst. It is done while
communicating with fast devices and cant be stopped or
slowed down.
In cycle stealing , one data word is transferred at a time.
CPU delays its operation for one cycle during which
DMA transfer takes place.
 DMA Controller
Address bus

Data bus Address bus

Data bus buffers
buffers

Internal bus
DMA select CS Address register

Register select RS
Read RD Word count register

Write WR
Control
Bus request BR logic Control register

Bus grant BG
DMA request
Interrupt Interrupt
to I/O device
DMA Acknowledge
 DMA Controller
It communicate with CPU through data bus
and control lines.
Registers in DMA are selected by CPU by
enabling DS and RS.
When BG=0, the CPU can communicate with
DMA register for read and write operation.
When BG=1 DMA communicate directly with
the memory.
 DMA Controller
Three registers
Address Register : Contains the address which specify
the location of memory to read and write, it is
incremented after each word is transferred to
memory.
Word count register : holds number of words to be
transferred. It is decremented by 1 after each word
transfer and regularly checked for 0.
Control register : specify the mode of the
transfer(read/write).
 DMA Transfer
Interrupt
BG Random access
CPU
memory (RAM)
BR

RD WR Address Data RD WR Address Data

Read control
Write control
Data bus
Address bus

Address
select

RD WR Address Data
DMA acknowledge
DS
RS Direct memory I/O
access (DAM) Peripheral
BR controller device
DMA request
BG
Interrupt
 DMA Transfer
I/O Device sends a DMA request.
DMAC activates the BR line.
CPU responds with BG line.
DMAC sends a DMA acknowledge to the I/O device.
I/O device puts a word in the data bus (for memory write).
DMAC write a data to the address specified by Address register.
Decrement Word count register.
When word count register reaches zero, control is given back to
the CPU.
Now I/O device can again request DMA.
Input-Output Processor
 Input-Output Processor
It is a processor with direct memory access capability
that communicates with I/O devices.
IOP is similar to CPU except that it is designed to
handle the details in I/O operations.
Unlike DMA which is initialized by CPU, IOP can fetch
and execute its own instructions.
IOP instructions are specially designed to handle I/O
operations.
Channel accesses memory by cycle stealing
CPU IOP COMMUNICATION