Lecture 5

Dataflow modeling
Instead of instantiating individual logic gates,
the designer thinks about the flow of data on
the nets.
Keyword is assign, e.g.
assign out = a&b;
Expression is always assigned to a net (scalar
or vector) but expression may involve register
or net, e.g. out should be wire but a and b
can be wire or reg
 A 4-bit Adder
i1
i2

i3

Gate Level model

wire i1, i2, i3;
and (i1,a0,b0);
and(i2,a0,cin);

 Data Flow model for a 4-bit adder
assign {cout, s[3:0]} = a[3:0] + b[3:0] + cin;

Explicit knowledge of gates is not required

Knowledge of available operators is required!
List of operators
 Arithmetic operators
Binary operators
Works on two operands
Performs arithmetic operations
Divide (/) gives the integer answer and ignores fraction
Modulus (%) gives the remainder from division
Takes the sign of the first operand
Example:
a= 4b 1000, b=4b0011, d=-3;
c=a/b; /*c= 4b0010 ( decimal value 2) fractional part is
ignored*/
e=a%d; //e=2, takes sign of the first operand
 Logical operators
Binary operators that return 1-bit value (1 for
true and 0 for false).
Exception is not (!) which is a unary operator but
still returns 1-bit value (1 or 0)