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circuit Synthesis
VHDL constructs versus automatic synthesis
What is synthesis?
Building blocks
Issues and example
Tools and targets
Hardware Description
Language (HDL)
Describe hardware not software
Description structure
Language strong syntax and type declarations
Concurrent
equations
Multiple Architectures for the same
entity
Xor described
behaviorally architecture EG2 of COMBO is
inside the process Begin
process (A, B, C)
Entity COMBO is begin
port (A,B,C: in bit; if (C = 0) then
D: out bit); D <= A nand B;
End COMBO; else
D<= A and B;
end if;
end process;
end EG2;
Multiple Architectures for the same
entity
Mix concurrent
statements and
architecture EG3 of COMBO is
processes signal T : bit;
Entity COMBO is begin
port (A,B,C: in bit; T <= A nand B;
D: out bit); p1 : process (T,C)
End COMBO; begin
D <= T xor C;
end process p1;
end EG3;
As we see, even for a very small circuit there are several descriptions possible. In case of large sequential
systems, this number is extremely large, how to select best? How to program in such a way that the system
will generate the best?
What is Synthesis?
Generate hardware from HDL
Eg. C <= A nand B gives
A
C
B
Is it that simple?
No, it is a very complex process in which time and
space can be rearranged and trade-offs investigated,
especially for sequential circuits.
What is Synthesis?
Watch out for these statements!
Flip-flops
Edge sensitive
entity FLIPFLOP is
architecture EG of FLIPFLOP is
begin
process (clk)
begin
if (clkevent and clk='1') then
Q <= D1 xor D2;
end if ;
end process;
end EG;
Descriptions of Synchronous
Set/Reset Flip Flops
Data and reset is NOT on sensitivity list.
Role of GUARDED
in synchronous FF
Synchronous Set/Reset Flip
Flops
Example:
library IEEE;
use IEEE.std_logic_1164.all;
entity FLIPFLOP is
Synchronous
port (D1, D2, reset, clk: in std_logic; reset
Q : out std_logic);
end FLIPFLOP;
architecture EG of FLIPFLOP is
begin
process (clk)
begin
if (clk'event and clk='1') then
if reset = '1' then
Q <= '0' ;
else
Q <= D1 xor D2;
end if ;
end if;
end process;
end EG;
Asynchronous Set/Reset Flip
Flops
Reset is ON sensitivity list.
library IEEE;
use IEEE.std_logic_1164.all;
entity FLIPFLOP is
architecture EG of FLIPFLOP is
begin
process (clk, reset)
begin
if reset = '1' then
Q <= '0' ;
elsif (clk'event and clk='1') then
Q <= D1 xor D2;
end if;
end process;
end EG;
Clock Enable Flip Flops
signal D, Q, enable, clk : bit ; enable
...
process (clk)
begin
if (clkevent and clk=1) then D Q
if (enable=1) then
D
Q <= D ;
end if ; clk
end if ;
end process ;
No sensitivity lists
No asynchronous reset D D Q
clk
Avoid undesired memory
elements
Assign values to variables before using them:
a := b and c;
d := a or b;
-- combinational network
We obtain a 3 bits
shift register
Explain why it is so This is strange For every variable
we have a ff.
Flip Flops inferred by
Variables
architecture EG of FLIPFLOP is The only difference here is
begin
order of assignments in
process (clk)
variable a,b : std_logic; process, here we have
begin variable assignments first.
if (clk'event and clk='1') then
a := D;
b := a;
Q <= b;
end if;
end process;
end EG; Remember that variables
are assigned immediately
library IEEE;
use IEEE.std_logic_1164.all;
entity tristate is
port ( D1, D2 , en1, en2 : in std_logic ;
Q : out std_logic);
end tristate ;
architecture EG of tristate is
begin
Q <= D1 when en1 = '1' else 'Z' ;
Q <= D2 when en2 = '1' else 'Z' ;
end EG ;
Flip-flops with Tristate Buffers
If output of FF or latch is tristated, enable line is also
tristated.
entity tristate is
port ( D, en, clk: in std_logic ;
Q : out std_logic);
end tristate ;
architecture EG of tristate is
begin
process (en, clk)
begin
if (en = '0') then
Q <= 'Z';
elsif (clk'event and clk = '1') then This is one more
Q <= D;
end if;
argument for using
end process; standard logic
end EG ; STD_LOGIC
Tri-State Buffer at the FFs output
Avoid FF in the path to control
the buffer
architecture DTri_enff of DTri is
begin
DTri_Lbl: process(Clk)
begin
if Clk'event and Clk = '1' then
if TriEnb = 0' then
Dout <= 'Z'; Din
SET
DOut
else D Q
Dout <= Din;
end if; Q
CLR
end if; TriEnb
end process DTri_Lbl; D
SET
Q
end DTri_enff; Clk
CLR
Q
library IEEE;
use IEEE.Std_Logic_1164.all; Tri-State Buffer at
entity DTri is
port(TriEnb : in Std_Logic;
the FFs output
Din : in Std_Logic;
Clk : in Std_Logic;
Dout : out Std_Logic);
end DTri;
architecture EG of tristate is
begin
Q <= D1 when en1 = '1' else "ZZZZZZZZ" ;
Q <= D2 when en2 = '1' else "ZZZZZZZZ" ;
end EG ;
clk
sig
result
1 0 what is state
encoding?
0 1
start wait found
0 0 0 1
...
Automaton of Mealy
signal RESET, CLK : BIT;
signal state_reg, next_state :
BIT_VECTOR (0 to 2);
...
process (Clk, Reset)
begin
if RESET then
state_reg <= 000; process (state_reg, I1, I2 ...)
elsif CLK=1 and CLKEvent then begin
state_reg <= next_state; case state_reg (0 to 2) is
end if; when 000 => if (I1 and ...) then
Next_state <= .....; Dout <= ..... ; end if;
when 001 => if (I1 and ...) then
end process;
Next_state <= .....; Dout <= ..... ; end if;
....
end case;
end process;
transitions : process
(present_state, input1)
Finite States Machine begin
case present_state is
when s0 =>
output1 <= '1' ;
entity test is
if (input1 = '1') then
port ( clk, input1, reset : in bit ;
next_state <= s0 ;
output1 : out bit );
else
end test ;
next_state <= s1 ;
end if ;
architecture EG of test is
type state_type is (s0, s1, s2) ; when s1 =>
output1 <= '0' ;
signal present_state, next_state :
next_state <= s2 ;
state_type ;
when s2 =>
begin
output1 <= '0' ;
registers : process (clk, reset)
if (input1 = '1') then
begin
next_state <= s0 ;
if (reset='1') then
else
present_state <= s0 ;
elsif clk'event and clk = '1' then next_state <= s2 ;
end if ;
present_state <= next_state;
end case ;
end if ;
end process ;
end process ;
end EG ;
Circuit
generated
Finite States Machine
Moore machine (shown) vs Mealy machine
State encoding control
Recommended type of FSM modeling
STATE_TYPE - Synchronous state change
process (Clk, Reset)
begin
Separate combinational and if RESET then
sequential to two processes state_reg <= S0;
elsif CLK=1 and CLKEvent then
state_reg <= next_state;
Separate transition function end if;
end process;
from output function (three
processes)
- Excitation and output functions
process (State_reg, I1, I2, .....)
signal state_reg, next_state : begin
STATE_TYPE;
case state_reg is
signal RESET, CLK : BIT;
when S1 => Next_state <= .....
....
Dout <= .....
when S2 => Next_state <= .....
Dout <= .....
.....
end case;
end process;
Finite States Machine
Case is better than if-then-else
Change variable
This is behavioral specification which is to signal
synthesizable to FPGAs and perhaps many PLDs
A word of caution.
Hardware realization of VHDL objects
Implementation of TMP :
wire
Implementation of TMP :
latch. Do you real want it?
Types / Operators 4 Rules
Unsigned, signed are arrays of std_logic (just like Std_Logic_Vector)
numeric_std overloads operators for use on types signed, unsigned, and their
combinations with integers. SLV is NOT in the picture.
The only library that lets you treat slvs as numbers is std_logic_unsigned (or
signed) which essentially just does the closely related type conversion for you.
tb : PROCESS
BEGIN
Sequential: encodes the states as a binary number (frequently in order of long paths)
000,001,010,011,100,101
Only one flip-flop is active, or hot, at any one time.
100000, 010000, 001000, 000100, 000010, 000001
One-Hot - The "One-Hot" encoding option will ensure that an individual state
register is dedicated to one state.
Only one flip-flop is active, or hot, at any one time.
One-hot encoding is very appropriate with most FPGA targets where a large
number of flip-flops are available.
It is also a good alternative when trying to optimize speed or to reduce power
dissipation.
State Encoding
Binary code
Gray code
Johnson code
one hot code
N 0f K code
Good guess
Additional software
Fail safe
State Encoding
Size : how many FFs are required to represent all your states?
current next
state state
State
Regs
Clk
Onehot Encoding
DFFs
readrq waiting High Energy
particle may
disrupt the
readcmd_latch_start
state of a FF
Comb leaving us in
Logic an illegal state.
readcmd_latch_wait
readcmd_latch_wehigh
If timing of readrq is such that it is right before the clock, if
delay paths are not matched, then we could enter illegal state
(wait ff could say Im zero but readcmd.. may not update to 1
Now we are wedged with current state = all zeros.
Illegal States
given our states : (red,yellow,green,fyellow,fred,turn_arrow)
case current_state is
when red => next_State <= turn_arrow;
when turn_arrow => next_state <= green;
when green => next_state <= yellow.
etc.
CLK
Some synthesis tools provide attributes for encoding machines that include :
safe,onehot ; safe,grey etc.
AND2
1
A 3
sigout
2 Y
U7 B
A2 1
A 3
OR2
Y
B2 2
B
AND2
andout2
Architecture pieces
begin
U6: and2 port map (a1,b1,andout1); component
U7: and2 port map (a2,b2,andout2); instantiations
AND2
1
A 3
sigout
2 Y
U7 B
A2 1
A 3
OR2
Y
B2 2
B
AND2
andout2
Anatomy of a CSA
sigout <= andout1 or andout2 after 5 ns;
This execution may schedule an event on the left hand side signal
(even at a later time if specified)
Anatomy of a CSA
sigout <= andout1 or andout2 after 5 ns;
From a Synthesizer Perspective :
The writer has written VHDL code that behaves a certain way (in this case, every
time either of the rhs signals change, sigout will be changed to be equal to the
logical or of the two. Computer : As a synthesizer my goal is to make some
hardware that acts this way also
an OR gate will do this but the synthesizer cant create a precise delay in any
target hardware, thus this is an error.
rewrite as : sigout <= andout1 or andout2;
Creating hardware that behaves a certain way is a difficult job, the writer has to
constrain what he writes so that it is possible for the
synthesis tool.
Processes
VHDL domains :
specifies when to
process (sensitivity list)
execute the process
declarations;
begin signals, variables valid
statements; inside the process
end process;
Process Examples
optional label
a
dougs_or : process(a,b)
begin b
c <= a or b;
end process dougs_or ; c
weird_or : process(b)
a
begin
b
c <= a or b;
end process weird_or ; c
What will synthesizer make for case 1? What hw would you make for case 2?
What will synthesizer make for case 2?
Process Examples
examp : process(b)
begin
b
c <= not b;
d <= not c; c
c <= b;
c <= not b; d
end process examp;
Process Executes in zero time, and signals are not updated until the process
suspends
Variables
signals are not useful for storing an intermediate computation in
the middle of a process, since they are not updated until the end.
For this, we use a variable.
process (x,y,z)
variable var_s1, var_s2 : std_logic;
begin
var_s1 := x and y;
var_s2 := var_s1 xor z;
sig_out <= var_s1 nand var_s2;
end process;
Signals
A signal defined at the architecture level is visible (readable and
writeable) in the processes defined in that architecture.
In general, use signals for values that go outside the process, and
variables for things that are just used to compute signal values.
6
a(3..0) 1
D0 S1
a(7..4) 2 S0
D1
b(3..0) 3 Y
5
D2
4
D3
4
U11
MX4 U10
4
sel(0) 1
U9
D Q
sel(1)
A 3 nibble_out
2 Y G
B
NAND2 DL1
Microprocessor I/O port
enable output drive
BUFF
2 Y 1
A
Registers :
DDR (Data Direction Register) 1 if port is an output, 0 if input
Output Data Register : if output, value in register is written to the port
if ddr = 1 then
outport <= data;
else
outport <= Z;
end if;
Looping to Replicate Hardware
mpu_porta : process (ddr,porta_reg)
begin
for i in 7 downto 0 loop
if ddr(i) = 1 then
porta_driver(i) <= porta_reg(i);
else
porta_driver(i) <= Z;
end if;
end loop;
end process mpu_porta;
Not necessary to define i, its definition was implicit (in this case
defaulted to integer)
complete form : for i in integer range 0 to 7 loop
Range Attributes
Specifying loop bounds explicitly is very inflexible when traversing
through an array.
you may not modify the loop counter within the loop
exit, next solve the problem of wanting to run through the loop a
variable number of times.
I dont recommend using these much, because as far as I can
tell, the XST synthesizer doesnt handle them well. Plus, they get
confusing as to what hardware you are making.
begin
-- some other stuff here ---
carry := '0';
BV := B;
process(vec)
variable result : std_logic_Vector(4 downto 0);
variable i : integer;
begin
result := "00000";
i := 0;
while i< 16 loop
exit when vec(i) = '1';
result := result + 1;
i := i + 1;
end loop;
count <= result;
end process;
Wait Statement
wait reserved word specifies when to suspend execution of the process and under
what conditions execution is to resume outputs are recomputed on wait:
wait for 20 ns; -- suspends the process, and waits for 20 ns.
You can either use wait statements or a sensitivity list, NOT BOTH. For the rest of
the class, excluding some special circumstances, I will use the sensitivity list form.
Some Synthesis Limitations
Process constraints:
1 3
D Q
2
CLK
DF1
process(clk)
begin
if (clr = 0) then ?
q<=0;
elsif rising_edge(clk) then
Q <= D;
end if;
end process;
Synchronous Design
In a purely synchronous system, all flipflops in the design are
clocked by the same clock.
CLK
DF1_CC
U32
U31
Y
A D Q
INV U32
INV
A
Y
D Q vs E
CLK
U33 CLK
DFE
DF1_CC U31
Y
A
INV U32
INV U32
U33
Y 1 D Q
A D Q A 3
2 Y E
U33 CLK B
CLK
AND2
DF1_CC DFE
Typical Synchronous System
Synchronous System Issues
Why Synchronous Logic? We can reduce the millions of steps
of analysis and timing verification of our system to a few
manageable ones:
D Q D Q D Q D Q
All FPGAs have some sort of solution like this. Global clocks are
obviously limited in number by the hardware. Making our designs
synchronous also helps us fit into this architecture.
Input Synchronization
Synchronize asynchronous inputs to system so that entire system
can be designed in a synchronous manner.
asynchronous signal
x32 x32
4
U34
1
A S 3
Y D Q
2
B
CLK
U33
MX2 DF1_CC
system clk 32 bit wide register
U32
synchronized to
asynchronous signal use in rest of design
D Q
CLK
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Inputs : use IEEE.STD_LOGIC_ARITH.ALL;
reset, clock, enable use IEEE.STD_LOGIC_UNSIGNED.ALL;
Outputs : entity bcdctr is
LSDigit, MSDigit (4 Port ( clk : in std_logic;
bits) reset : in std_logic;
en : in std_logic;
bcd : out std_logic_vector(7 downto 0));
end bcdctr;
Simple example : 2 digit BCD ctr
this is the hardware that we envision. Knowing what hardware you
want to build is preferable to cranking VHDL.
architecture behavior of bcdctr is
signal mdigit : std_logic_vector(3 downto 0);
en signal ldigit : std_logic_vector(3 downto 0);
ldigit
begin
counter 0-9 lcnt : process(clk,reset)
clk
begin
if reset = 0 then
en and ldigit <= 0000;
elsif rising_edge(clk) then
ldigit =9 if en = 1 then
mdigit
if ldigit = 1001 then
counter 0-9 ldigit <= 0000;
clk
else ldigit <= ldigit + 0001;
end if;
end if;
end if;
end process lcnt;
Simple example : 2 digit BCD ctr
en and mcnt : process (clk,reset)
ldigit =9 begin
mdigit if reset='0' then
counter 0-9 mdigit <= "0000";
clk elsif clk='1' and clk'event then
if (ldigit="1001") and (en='1') then
if mdigit = 1001 then
mdigit <= 0000";
else mdigit <= mdigit + 0001;
end if;
end if;
end if;
end process mcnt;
end behavior;
In Webpack (Synthesis Rept)
Synthesizing Unit <bcdctr>.
Related source file is
C:/WINDOWS/Desktop/school/vhdlclass/projectsolutions/demo/demo.vhd.
Found 4-bit up counter for signal <ldigit>.
Found 4-bit up counter for signal <mdigit>.
Summary:
inferred 2 Counter(s).
Unit <bcdctr> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Counters : 2
4-bit up counter : 2
=========================================================================
In Webpack (Rough Timing)
TIMING REPORT
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP | 8 |
-----------------------------------+------------------------+-------+
Timing Summary:
---------------
Speed Grade: -5
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
To run functional simulation
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