Design of a high gain integrated

operational amplifier using bipolar

junction transistor

Presented by:
Anupam Boro.(ELB10028)
Uttam Chetri.(ELB10059)
Chunchu Kartik.(ELB09046)
Guided by:
Ms. Priyanka Kakoty
Asst. Prof., Dept. of E.C.E., Tezpur university.
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 Abstract
Operational amplifiers (op-amps) serve as the basic building blocks
in almost every analogue and mixed-signal electronic circuit. It is the
main bottleneck in an analogue circuit. When it comes to electronic
tenability, operational amplifiers have proven to be the best candidate
for implementation.
In linear integrated circuit design, design of a high gain (open loop)
operational amplifier by using less possible passive component is a
important step so that op-amp can be designed in less area and closed
loop gain become nearly insensitive to its varying parameters like
temperature, frequency, mass production technique etc.
In this project a multistage BJT operational amplifier having 3 stages
namely- Differential stage, Level Shifter and the Output stage is
designed with less possible passive components. The various
parameters of the operational amplifier as Gain, CMRR, Bandwidth,
etc. are theoretically calculated and simulation is also carried out in
MULTISIM 12.0 version to verify the calculated values.
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 Introduction
Op amps are key elements in analogue systems mostly
used in electronic devices in consumer, industrial &
scientific devices.
Op amp is a type of differential amplifier, which generates
at the output an amplified replica of the voltage across
the input terminal.
Ideally they perform the function of a voltage controlled
current source, with an infinite voltage gain so that when
negative feedback is applied, the closed-loop transfer
function is practically independent of the gain of the
operational amplifier.
Op-amps can be used two ways
1.Open-loop mode.
2.Feedback mode.
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Why high open loop gain?
Practically this gain is some large value of few
thousands
This gain varies with temperature, power supply etc.
This gain needs to be controlled so that op-amp does
not go into oscillation.
Because of area it is also necessary to design by
using least possible passive components.

Fig. :Block diagram of a typical op-amp. 4

 When operated in closed loop
Closed loop gain ,

AOL ---- open loop gain; ---- feedback factor.

If the open loop gain is infinity then the equation can
be written as:
Now which mostly consists of passive components
, can be designed appropriately in sensitive to any
parameter.
so, high open loop gain is necessary.

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The circuit design:

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 The various stages:
1st stage : a differential amplifier with active
load and current source.
reference current
=1mA.

This reference current

is used to bias each
transistor, such that
no transistor goes to
saturation.
Bias current of 0.5mA
is used to bias the 1st
Stage. 7
Limit on input signal Vin:
Vin max = VQ3=Vcc - V
VQ6 cant drop below -VEE + 1.4V
Vin min = -VEE + 2V
so, -8.6V Vin 9.3V
Which is the common mode range.
Maximum of Vq4 can be 9.3V
DC voltage of collector of Q6
Vin-0.7 = -VEE +0.7
Vin = -10 + 1.4 = -8.6
-8.6V VCM 9.3V
So, 1st stage determines the common mode range.
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2nd stage: 3rd stage:
A PNP common emitter A NPN Common
with current source to collector stage with a
get maximum gain out of resistor to get the
it. desired attenuation.

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Output stage.
A NPN common collector stage to get low o/p
resistance. Output swing limit:
Maximum of VQ7 before Q7
goes into saturation,
VQ7 max =Vcc - 0.7

Also, VQ7 max =Voutmax + 0.7

Gives,
Voutmax = Vcc 1.4 V =8.6V

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Minimum of output signal cannot fall below
the base voltage of Q10, i.e
Voutmin = -VEE + 0.7
Voutmin = -10 + 0.7 =-9.3V
Which gives us o/p swing limit as
below..
-9.3V Vout 8.6V
Or,
A symmetric swing limit of 8.5V.
So, o/p stage gave us the maximum
possible swing limit.

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 Calculated parameters:
Gain(dB) CMRR(dB) i/p o/p DC Power o/p offset Common mode o/p swing limit.
impedance impedance consumed. volt. range.

149.9 68.5 22k 25 80 mW 0.3V -8.6V to 9.3V -9.3V to 8.6V

Simulation result:
Gain(dB) CMRR(dB) gain bandwidth 3dB cut-off Slew rate.(V/S)
product.(MHz) frequency(kHz)

107.85 57.68 120 12 0.95

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 Simulated waveforms.
Simulation with transistor model
2N2222A(npn), 2N3906(pnp)
(VA=140V,=200)

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Fig.1 : Differential mode waveforms.
Fig.2: common mode waveforms

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Slew rate measurement.

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Frequency response.

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 Discussion:
1st stage Gain = gm2r02 , gain = Ic2/rc2 * VA2/Ic2.
2nd stage gain = gm7r07 , gain = Ic7/rc7 * VA7/Ic7.
Total gain AVT = gm2r02 gm7r07.
also gain VA (early voltage)

Since, gain dependency is on device parameter vA

so with the same device parameter to get higher
gain we must cascade another stage.

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 Conclusion
If VA= 500V, gain = 113dB, And it is found after that,
there is no increase in gain with early Voltage.
Gain can be increased by cascading another stage.
This increases the order of the system..
System will definitely oscillate at some frequency.
So there exists the need of a compensation circuit
which could increase the gain substantially , and
simultaneously optimizing all parameters in the
design.
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 Future prospect
From this project we got the maximum
possible gain with the given transistor
parameter. So in order to increase the open
loop gain further we will cascade another
Stage with necessary compensation circuit so
that we close approximate the ideal infinite
open loop gain without making the op-amp to
oscillate when its operated in closed loop
mode.

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