G.

Kanaka Durga Bhavani

15ME1D5704

Under the Esteemed Guidance of

Mr. M. Rama Krishna M.Tech

Associate Professor

Department of ECE
Objective

To design a radix-8 encoded booth multiplier which

minimize the delay, power consumption and area by
decreasing the Partial product rows over the
existing Radix-4 Booth encoded multiplier.
Introduction
Literature Survey
Existing System
Radix-4 booth encoder performs the process of encoding
the multiplicand based on multiplier bits.
Multiplier Recoded
Radix-4 partial products generation bits Operation on
Multiplicand
01001011- multiplicand
01000111- multiplier 000 0xM
0 1 0 0 0 1 1 1 |0 001 +1xM
+1M 0M +2M -1M 010 +1xM
011 +2xM
-1M 1 1 1 1 1 1 1 0 1 1 0 1 0 1 Partial Product 100 -2xM
+2M 0 0 0 0 1 0 0 1 0 1 1 0 x x rows 8/2=4
0M 0 0 0 0 0 0 0 0 0 0 x x
101 -1xM
+1M 0 1 0 0 1 0 1 1 x x 110 -1xM

01010011001101 111 0xM

Contd..
It will compare 3 bits at a time with overlapping
technique. Grouping starts from the LSB, and the first
block only uses two bits of the multiplier and assumes
a zero for the third bit.
The Normal Binary Multiplication generates n partial
products rows. Note n is the multiplier bits.
Where as in the Radix 4 Booth Encoding the
generation of the partial products is reduced to half, i.e
n/2. For 8 bit multiplication the PP rows generated are
4.
Non Redundant Radix 4 Multiplier

System Architecture of Non Redundant Radix 4 Multiplier

Why We Need Radix 8?
The solutions of realizing high speed multipliers is to
reduce the partial products.
The Radix-4 Booth Encoding will reduce the partial
product rows to half (n/2), where as in Radix 8 Booth
Encoding, the partial products rows are reduced to
n/3.
Which in turn reduces the area required and delay and
offer a speed operation.
Proposed Method
Radix-8 Booth recoding applies the same algorithm as
that of Radix-4, but now we take quartets of bits
instead of triplets. Each quartet is codified as a signed
digit using Radix 8 Booth Encoding. Radix-8 algorithm
reduces the number of partial products to n/3, where n
is the number of multiplier bits. Thus it allows a time
gain in the partial products summation.
Radix-8 Booth Encoding
Multiplier Bits Recoded Operation on
0M means multiplicand multiplied by
Yi+ 2 Yi+ 1 Yi Yi 1 multiplicand, M
zero.
0 0 0 0 0M
+1M means product still remains the
0 0 0 1 +1M
same as the multiplicand value. .
0 0 1 0 +1M
0 0 1 1 +2M +2M means shift left the multiplicand
0 1 0 0 +2M value one place
0 1 0 1 +3M +4M means just shift left the
0 1 1 0 +3M multiplicand by two place.
0 1 1 1 +4M -1M means that the product is the
1 0 0 0 -4X twos complement form of the
1 0 0 1 -3M Multiplicand
1 0 1 0 -3M
-2M means shift left one bit the twos
1 0 1 1 -2M
complement of the multiplicand value
1 1 0 0 -2M
1 1 0 1 -1M -4M shift left two bit the twos
1 1 1 0 -1M complement of the multiplicand value
1 1 1 1 0M
Hard Multiple
3M is hard multiple since
cant be generated by simple
shifting and complementing
of multiplicand.
To generate 3M with 8-bit
words we only have to add
2M+M, that is, to add the
number with the same
number shifted one position
to the left.
Radix-8 Booth Multiplication
Radix-8 partial products generation
01000111- multiplicand
01001011- multiplier

0 0 1 0 0 1 0 1 1 |0 4 bit grouping

+1M +1M +3M

11010101 (+3M)
01000111xxx (+1M) Partial product n/3
1000111xxx (+1M)
10100110 01101
Block Diagram of Radix-8
This is used to generate the Booth Booth Selector will generate the
Selection signals and Sign Bit Partial Products
Radix 8 Partial Product Generator
Carry Save Adder
CSA(carry save adder) & Accumulation: This is used to add the

partial products generated above and accumulate them. Here

accumulation is carried out along with the addition of the partial

products. As a result, n-bit Sum ,Carry, and Z (the result from adding

the lower bits of the sum and carry) are generated. These three

values are fed back and used for the next accumulation.
Carry Propagate Adder
Final adder: This is used produce final result

(i.e) P[2n-1:n] which is generated by adding S

and C in the final adder and combined with

P[n-1:0] that was already generated.

Advantages of Proposed System
The RNS system offer a unique parallelism feature
that make arithmetic operations (Such as Addition,
subtraction and modulation) very easy to handle.
Reducing chip area and Perform increasing speed
High-Speed
Carry free
Error Detection and Correction Capability
Fault Tolerant
Parallel Operation
Medium Security
Low Power Circuits
Applications of Radix 8 Multiplier
Multimedia and communication systems

Real-time signal processing Such as

Audio signal processing,

Video/image processing, or large-capacity data processing

RSA Algorithm

Image Processing

Digital Signal Processing

Digital Filtering

Error Detection and Correction

Results
RTL Schematic
Timing Report
=================================================================
Timing Summary:
--------------------------------------------------------------------------------------------------------------
Speed Grade: -4

Minimum period: No path found

Minimum input arrival time before clock: 24.020ns
Maximum output required time after clock: 4.283ns
Maximum combinational path delay: No path found

Total : 24.020ns (13.529ns logic, 10.491ns route)

(56.3% logic, 43.7% route)

Timing Detail:
--------------------------------------------------------------------------------------------------------------
All values displayed in nanoseconds (ns)
=================================================================
Simulation Results
 196
NR4SD NR8SD
186

109 106

33
26

Slices LUT IOB

 NR4SD NR8SD
29.79

24.02

Delay in ns
 However, The Radix-8 multiplier reduces the
previous add and also obtained a time
advantage compared to a Radix-4
architecture.
The delay is decreased to 19.31% When
compared to existing System, hence the speed
is increased and the area decreased.
Conclusion
It can be useful to apply a radix-8 architecture
in high-speed multipliers for specific purpose
because of the gain in time and number of
transistors compared to the conventional radix-4
recoding architecture.
Memory needs are increased in a 9.5% while
time delay decrease in the previous adder can
be estimated in a 19.31%.
The overall multiplication time can be reduced
with this radix-8 architecture for specific
purpose.
References
Tsoumanis, N. Axelos, N. Moshopoulos, G. Zervakis and K.
Pekmestzi, Pre-Encoded Multipliers Based on Non-Redundant
Radix-4 Signed-Digit Encoding, IEEE Transactions on
Computers, 2015
Chip Hong Chang and Ramya Muralidharan, Radix-4 and
Radix-8 Booth Encoded Multi Modulus-Multiplier, IEEE
Transaction on Circuit and Systems I: Regular, 2013
Eben Sophia p., Jackuline Moni D., Design of low power
and high speed Configurable Booth Multiplier, IEEE
Transaction, 2011
Fabrizio Lombardi, Fei Oiao, Honglan Jiang, Jie Han,
Approximate Radix-8 Booth Multipliers for Low-Power and
High-Performance Operation, IEEE Transactions on
Computers Volume: 65, Issue: 8, 2016