Low-Noise Amplifier

1
 RF Receiver

Antenna

BPF1 LNA BPF2 Mixer BPF3 IF Amp

Demodulator

RF front end LO

2
 Low-Noise Amplifier
First gain stage in receiver
Amplify weak signal
Significant impact on noise performance
Dominate input-referred noise of front end
NFsubsequent 1
NFfrontend NFLNA
GLNA
Impedance matching
Efficient power transfer
Better noise performance
Stable circuit

3
 LNA Design Consideration
Noise performance
Power transfer
Impedance matching
Power consumption
Bandwidth
Stability
Linearity

4
 Noise Figure
Definition
SNRin Sin N in
NF
SNRout S out N out

As a function of device
N device G N source
NF
G N source

G: Power gain of the device

5
 NF of Cascaded Stages
Sin/Nin Sout/Nout

G1, N1, Gi, Ni, GK, NK,

NF1 NFi NFK
NF2 1 NF3 1 NFK 1
NF 1 NF1 1 ...
G1 G1G2 G1G2 ...GK 1
Overall NF dominated by NF1

[1] F. Friis, Noise Figure of Radio Receivers,

Proc. IRE, Vol. 32, pp.419-422, July 1944.

6
Simple Model of Noise in MOSFET
k
Flicker noise g V 2
( f )
WLCox f
Vg
Dominant at low frequency
Id
Thermal noise I d2 ( f ) 4kTg g m
g: empirical constant
2/3 for long channel
much larger for short channel
Vi PMOS has less thermal noise

Input-inferred noise
g k
Vi 2 ( f ) 4kT
gm WLCox f
7
 Noise Approximation

Noise spectral
density

1/f noise
Thermal noise
dominant
Thermal noise

Frequency
Band of interest
8
Power Transfer and Impedance Matching

Power delivered to load

2
Rs Vs
jXs jXL Pdel RL
Rs jX s RL jX L
Vs I V RL
Maxim available power
VsVs*
Pmax PL R R , X X 0
s L s L
4 Rs
Impedance matching
Load and source impedances conjugate pair
Real part matched to 50 ohm

9
Available Power

Equal power on load

and source resistors

10
 Reflection Coefficient
Rs V IZ L
jXs jXL
Vs I V RL V IZ s
a
2 Rs

I I * ( Z L Z L* ) V IZ s*
Pdel b
2 2 Rs
VsVs* (V IZ s )(V IZ s )*
Pmax aa*
4 Rs 4 Rs b Z L Z s*

(V IZ s* )(V * I *Z s ) a ZL Zs
Pref Pmax Pdel bb*
4 Rs
11
Reflection Coefficient

No reflection
Maximum power transfer

12
 S-Parameters
Parameters for two-port system analysis
Suitable for distributive elements
Inputs and outputs expressed in powers
Transmission coefficients
Reflection coefficients

13
 S-Parameters
a1 b2
S21

S11
S22

S12

b1 a2
b1 S11a1 S12a2
b2 S 21a1 S 22a2
14
 S-Parameters
b1 S11 input reflection coefficient with
S11 the output matched
a1 a 20
b2 S21 forward transmission gain or
S 21
a1 a 20 loss

b1
S12 S12 reverse transmission or
a2 a10 isolation
b2
S 22 S22 output reflection coefficient with
a2 a10 the input matched

15
 S-Parameters
I1 I2
Z1 S Z2
Vs1 V1 V2 Vs2

V1 I1Z1* V2 I 2 Z 2* Re( Z1 )
S11 S21
V1 I1Z1 V V1 I1Z1 Re( Z 2 ) V
s 2 0 s 2 0

V1 I1Z1* Re( Z 2 ) V2 I 2 Z 2*
S12 S22
V2 I 2 Z 2 Re( Z1 ) V V2 I 2 Z 2 V
s 1 0 s 1 0

16
 Stability Condition

Necessary condition
1 | S22 |2 | S11 |2 | S |2
K 1
2 | S12S21 |
where S S11S22 S12S21
Stable iff
| S |2 L L 1
where | S11 |2 | S22 |2
L | S12S21 |
2

17
 A First LNA Example
io Assume
Rs
No flicker noise
Vs
ro = infinity
Cgd = 0
Reasonable for appropriate
bandwidth
Rs 4kTRs Effective transconductance
io g m Zin
Gmeff
Vs Vgs
gmVgs 4kTggm Vs Rs Zin

18
 Power Gain
Voltage input
Current output
2
ii *
g m Z in
G | Gmeff |
o o 2

VsVs*
Rs Z in
2 2
g m 1 ( jC gs ) gm

Rs 1 ( jC gs ) 1 jRs C gs
2
g 2
T 1
m

1 ( Rs C gs )
2 2
Rs

19
 Noise Figure Calculation
Power ratio @ output
Device noise + input-induced noise
Input-induced noise
N device G Nin 4kTg g m
NF 1
G Nin g m2
4kTRs
1 2 ( RsCgs ) 2
g
1 (1 2 Rs2Cgs2 )
Rs g m
g 2 gm
1 gRs g m T
Rs g m ( g m / Cgs )2 Cgs

20
Unity Current Gain Frequency

iin Device iout

iout Ai
Ai
iin
i fT
Ai out T 1
T
iin T 0dB
frequency f

21
 Small-Signal Model of MOSFET
i2
i1
Cgs
V1 V2 Cgd
rds
Cdb
i1 i2
Rg Cgd Rg: Gate resistance
Cgs Vgs Cdb ri: Channel charging
V2 resistance
V1 ri rds
gmVgs
22
 T Calculation
i1 Rg Cgd i2 i1 Rg Cgd i2

Cgs Vgs Cdb Cgs Vgs

gmVgs gmVgs
V1 ri rds V1 ri

I1 s (C gs C gd ) s 2 riCgsC gd
Y11
V1 V 0 1 s (Cgs Cgd ) Rg sriC gs s 2 Rg riC gsC gd
2

I2 g m (1 sriCgs ) sC gd s 2 riCgsCgd
Y21
V1 V 0 1 s (Cgs Cgd ) Rg sriCgs s 2 Rg riCgsCgd
2

23
 T of NMOS and PMOS
Set: 0.25um CMOS Process*
Y11 ( j T )
1
Y21 ( j T )

Solve for T
gm
T gm
Cgs Cgd

[2] Tajinder Manku, Microwave CMOS - Device Physics and Design,

IEEE J. Solid-State Circuits, vol. 34, pp. 277 - 285, March 1999.
24
 Noise Performance
g 2
NF 1 g Rs g m 2
Rs g m T
Low frequency
Rsgm >> g ~ 1
gm >> 1/50 @ Rs = 50 ohm
Power consuming
CMOS technology
gm/ID lower than other tech
T lower than other tech

25
 Review of First Example
No impedance matching
Capacitive input impedance
Output not matched
Power transfer
S11=(1-sRCgs)/(1+sRCgs)
S21=2Rgm/(1+sRCgs), R=Rs=RL
Power consumption
High power for NF
High power for S21

26
 Impedance Matching for LNA
Resistive termination
Series-shunt feedback
Common-gate connection
Inductor degeneration

27
 Resistive Termination
io
Rs 4kT/Rs 4kT/RI 4kTggm

Vs RI Is Rs RI Vgs
gmVgs
Current-current power gain
2
gm
G
1 / Rs 1 / RI j Cgs
Noise figure
2
Rs g Rs 1 1 2
NF 1 g g m Rs 2
RI g m Rs RI T

28
Comparison with Previous Example
Previous example
g 2
NF 1 g Rs g m 2
Rs g m T

Resistive-termination
2
Rs g Rs 2
NF 1 1 g g m Rs 2
RI g m Rs RI T

Introduced by input
resistance Signal attenuated

29
Summary - Resistive Termination
Noise performance
Low-frequency approximation
Input matched Rs = RI = R
4g
NF 2
gm R
Broadband input match
Attenuate signal
Introduce noise due to RI
NF > 3 dB (best case)

30
 Series-Shunt Feedback
RF Broadband matching
RL
Rs
( RF RL )(1 g m Ra sRaCgs )
Rin
Vs 1 g m ( RL Ra ) s( Ra RF RL )Cgs
Ra (1 g m Ra )( RF Rs )
Rout
1 ( g m sC gs )( Rs Ra )
sC gs ( Ra RF Rs RF Ra Rs )
Rs RF iout
1 ( g m sC gs )( Rs Ra )
RL
Cgs Vgs gmVgs Could be noisy
Vs
Ra

31
 Common-Gate Structure
4kTggm
RL
Rs RL
Rs 4kTRs

Vs Vgs gmVgs

I out
Geff
Vs Rs 4kTRs RL
gm gm

1 g m Rs sRs Cgs Vs Vgs gmVgs

4kTggm

32
 Input Impedance of CG Structure
Input impedance
Yin=gm+sCgs

Input-impedance matching
Low frequency approximation
Direct without passive components
1/gm=Rs=50 ohm

33
Noise Performance of CG Structure
2 g m2
G Geff
(1 g m Rs ) 2 2 ( Rs Cgs ) 2

N device G N in 4kTg g m
NF 1
G N in g m2
4kTRs
(1 g m Rs ) 2 2 ( RsCgs ) 2
g
1
Rs g m
(1 g R
m s ) 2
2 2 2
Rs Cgs
2
1 4g g 2
T

Signal attenuated
34
 Power Transfer of CG Structure
Rs = RL = R = 50 ohm
Zin Z s* 1 g m Rs sRsCgs
S11
Zin Z s 1 g m Rs sRsCgs
sRsCgs

2 sRsCgs
2 RL g m
S21 2 RLGeff
1 g m Rs sRsCgs
2

2 sC gs
S11=0, S21=1 @ Low frequency

35
 Summary CG Structure
Noise performance
No extra resistive noise source
Independent of power consumption
Impedance matching
Broadband input matching
No passive components
Power consumption
gm=1/50
Power transfer
Independent of power consumption

36
 Inductor Degeneration Structure
Zin
Rs Lg iout
Rs Lg
iin Cgs Vgs gmVgs
Vs Vin
Ls Vs Ls

1
Vin I in sLg I in ( I in g mVgs ) sLs
sC gs
1 1
I in sLg I in ( I in g m I in ) sLs
sC gs sC gs
1 g m Ls
I in s ( Lg Ls ) Zin
sC gs Cgs
37
 Input Matching for ID Structure
Zin
Rs Ls Lg iout

gmLs/Cgs Cgs Vgs gmVgs

Vs

1 gm Ls
Zin=Rs Zin s( Lg Ls )
sCgs Cgs
1
IM{Zin}=0 2

( Lg Ls )Cgs
0

gm Ls
RE{Zin}=Rs Rs
Cgs

38
 Effective Transconductance
Zin
Rs Ls Lg iout

gmLs/Cgs Cgs Vgs gmVgs

Vs

I out g m ( sC gs )
Geff
Vs Rs Zin
gm

1 s( RsCgs g m Ls ) s 2Cgs ( Lg Ls )

39
 Noise Factor of ID Structure
2 g m2
G Geff
[1 2Cgs ( Lg Ls )]2 2 ( RsCgs g m Ls ) 2
= 0 @ 0
Calculate NF at 0
N device G Nin 4kTg g m
NF 1
0
G Nin g m2
4kTRs 2
( RsCgs g m Ls )2
g
1 2 ( RsCgs g m Ls )2
Rs g m

40
 Input Quality Factor of ID Structure

I R L Stored power
Q
Lost power
C
V I I * C 1

II R*
CR

1 1
Rs Ls Lg Qin
CR C gs ( Rs g m Ls / C gs )
Vs gmLs/Cgs Cgs 1 1

( Rs C gs g m Ls ) 2Rs C gs

41
 Noise Factor of ID Structure
Increase power transfer
1 gmLs/Cgs = Rs
Qin
( RsCgs gm Ls )
Decrease NF
NF gmLs/Cgs = 0
0

g
1 2 ( RsCgs g m Ls )2
Rs g m Conflict between
g 1 Power transfer
1
Rs g m Qin2 Noise performance

42
 Further Discussion on NF
Frequency @ 0
NF 2 ~= 1/Cgs/(Lg+Ls)
0

g Input impedance
1 2 ( RsCgs g m Ls ) 2 matched to Rs
Rs g m
4( g m Ls ) 2 1 RsCgs=gmLs
1 g
Rs g m C gs ( Lg Ls ) Ls Rs T
4g Ls Suitable for hand
1
Lg Ls calculation and design
Large Lg and small Ls
Ls Lg 1 02Cgs
43
 Power Transfer of ID Structure
Rs = RL = R = 50 ohm
Zin Z s* 1 s Cgs ( Lg Ls ) sg m Ls sRsCgs
2

S11
Z in Z s 1 s 2Cgs ( Lg Ls ) sg m Ls sRsCgs
1 s 2Cgs ( Lg Ls )

1 s ( g m Ls RsCgs ) s 2Cgs ( Lg Ls )

2 gm RL
S21 2Geff RL
1 s( RsCgs gm Ls ) s 2Cgs ( Lg Ls )
1
@ 20 Qin
1
( Lg Ls )Cgs ( RsCgs gm Ls )

2 g m RL T RL
S11 0; S 21 j 2 g m RLQin j
j0 ( Rs Cgs g m Ls ) 0 Rs 44
Computing Av without S-Para
Rs Lg

Vs
Ls

At resonance and imput match : Z in Rs

I in Vs 2 Rs ; I o g mVgs g m I in j0C gs
I o g mVs 2 j0C gs Rs jVsT 20 Rs
Vo T 1/ 2
Av j
Vs 0 Rs (Yo Yo )
45
 Power Consumption
Cox W
P I DVDD (Vgs VT ) 2 VDD
2 L
W 2
g m Cox (Vgs VT ) Cgs CoxWL
L 3

Cox Vgs VT
g m2 L2 3 W 2 g m Ls RsCgs
Rs gm
C gs 2 L Cgs Ls

g m2 L2 L2 Rs2 L2 Rs2 VDD

P VDD C gsVDD
3C gs 3 Ls
2
3 L2s 02 ( Lg Ls )
2
L2 2
1 T L2VDD 1 L2 Rs2 VDD
P T
C gsVDD

2 3
3 3 0 ( Lg Ls ) 3 0 Ls (1 Lg / Ls )

46
 Power Consumption
L2 Rs2 1 4g Ls
P 2 3 NF 1
0 Ls (1 Lg / Ls ) 0
Lg Ls

Technology constant
L: minimum feature size
: mobility, avoid mobility saturation region
Standard specification
Rs: source impedance
0: carrier frequency
Circuit parameter
Lg, Ls: gate and source degeneration inductance

47
 Summary of ID Structure
Noise performance
No resistive noise source
Large Lg
Impedance matching
Matched at carrier frequency
Applicable to wideband application, S11<-10dB
Power transfer
Narrowband
Increase with gm
Power consumption
Large Lg

48
 Cascode

LL Isolation to improve S12

Vo @ high frequency
Vbias M2 Small range at Vd1
Reduced feedback effect
Rs Lg Vd1
of Cgd
M1
Vs Improve noise
Ls performance

49
 Rs Lg Vo
LL Vo

Rs Lg
Cgs Vgs gmVgs
M1
Vs Vs Ls LL
Ls

50
 LNA Design Example (1)
Vdd
Lvdd Lb2 Cb2 V
out

M4 Output
Ld Lout
bias
Vbias
M2 M3
Lb1 Tm
Rs
M1
Lg Lgnd
Cb1
Vs Cm
Ls
Input
bias Off-chip
matching
[3] D. Shaeffer and T. Lee, A 1.5-V, 1.5-GHz CMOS low noise amplifier, IEEE J. Solid-
State Circuits, vol. 32, pp. 745 759, May 1997. 51
 LNA Design Example (1)
Supply
filtering Lvdd

M4
Ld Lout

Vbias
M2 M3
Lb1 Tm
Rs
M1
Lg Lgnd
Cb1
Vs Cm
Ls

Unwanted
parasitics
[3] D. Shaeffer and T. Lee, A 1.5-V, 1.5-GHz CMOS low noise amplifier, IEEE J. Solid-
State Circuits, vol. 32, pp. 745 759, May 1997. 52
 Circuit Details
Two-stage cascoded structure in 0.6 m
First stage
W1 = 403 m determined from NF
Ls accurate value, bondwire inductance
Ld = 7nH, resonating with cap at drain of M2
Second
4.6 dB gain
W3 = 200 m

53
54
 LNA Design Example (2)
NF = 1 + K/gm
gm = gm1 + gm2

M2 IB1
RB Vout1
IREF NL
RX
M4 VB1
VRF Ns M1 Off-chip
M5
Cs CX matching
Off-chip M7
CB
matching M3 M6

[4] A. Karanicolas, A 2.7-V 900-MHz CMOS LNA and Mixer, IEEE J. Solid-State
Circuits, vol. 31, pp 1939 1944, Dec. 1996. 55
Simplified view

56
 LNA Design Example (2)

M8 M2 IB1
RB Vout1
IREF NL
RX
M4 VB1
VRF Ns M1 M5
Cs CX

M7
CB
M3 M6
Bias
feedback
[4] A. Karanicolas, A 2.7-V 900-MHz CMOS LNA and Mixer, IEEE J. Solid-State
Circuits, vol. 31, pp 1939 1944, Dec. 1996. 57
 LNA Design Example (2)

M8 M2 IB1
RB Vout1
IREF NL
RX
M4 VB1
VRF Ns M1 M5
Cs CX

M7
CB
M3 M6
Bias
feedback
[4] A. Karanicolas, A 2.7-V 900-MHz CMOS LNA and Mixer, IEEE J. Solid-State
Circuits, vol. 31, pp 1939 1944, Dec. 1996. 58
 LNA Design Example (2)

VA IB1
M8 M2
RB Vout1
IREF NL
RX
M4 VB1
VRF Ns M1 M5
Cs CX

M7
CB
M3 M6
Bias
DC output = VB1
feedback
[4] A. Karanicolas, A 2.7-V 900-MHz CMOS LNA and Mixer, IEEE J. Solid-State
Circuits, vol. 31, pp 1939 1944, Dec. 1996. 59
60
 LNA Design Example (3)
Objective is to design tunable RF LNA that
would:

Operate over very wide frequency range with very fine

selectivity
Achieve a good noise performance

Have a good linearity performance

Consume minimum power

61
 LNA Architecture
The cascode architecture
provides a good input
output isolation
Transistor M2 isolates the VDD
Miller capacitance R1
Input Impedance is obtained LD
using the source M3 Matching
degeneration inductor Ls Network
R2 M2
Gate inductor Lg sets the Output to
resonant frequency Mixer
M1
The tuning granularity is Input to LNA LG
achieved by the output LS
matching network

62
 Matching Network
The output matching tuning
network is composed of a
varactor and an inductor.
The LC network is used to
convert the load impedance
into the input impedance of
the subsequent stage.
A well designed matching
network allows for a
maximum power transfer to
the load.
By varying the DC voltage
applied to the varactor, the
output frequency is tuned to
a different frequency.
63
 Simulation Results - S11
The input return loss
S11 is less than 10dB
at a frequency range
between 1.4 GHz and
2GHz

Input return loss

64
 Simulation results - NF
The noise figure is 1.8
dB at 1.4 GHz and rises
to 3.4 dB at 2 GHz.

Noise Figure

65
 Simulation Results - S22
By controlling the voltage applied to the varactor the output frequency
is tuned by 2.5 MHz.
The output return loss at 1.77 GHz is 44.73 dB and the output return
loss at 1.7725 GHz 45.69 dB.

S22 at 1.77 GHz S22 at 1.7725 GHz

66
 Simulation Results - S22
The output return loss at 2 GHz is 26.47 dB and the output return
loss at 1.9975 GHz 26.6 dB.

S22 at 2 GHz S22 at 1.9975 GHz

67
 Simulation Results - S21
The overall gain of
the LNA is 12 dB

S21 at 1.4025 GHz

68
 Simulation Results - Linearity
The third order input intercept is 3.16 dBm
-1 dB compression point ( the output level at which the actual gain
departs from the theoretical gain) is 12 dBm

IIP3 -1dB compression point

69
 From an earlier slide:
k
Flicker noise g V 2
( f )
WLCox f
Vg
Dominant at low frequency
Id
Thermal noise I d2 ( f ) 4kTg g m
g: empirical constant
2/3 for long channel
much larger for short channel
Vi PMOS has less thermal noise
Input-inferred noise
g k
Vi 2 ( f ) 4kT
gm WLCox f

Not accurate for low voltage short channel devices

70
 Modifications
Thermonoise
gm
I ( f ) 4kTg g do 4kTg
2

g is called excess noise factor

= 2/3 in long channel
= 2 to 3 (or higher!) in short
channel NMOS (less in PMOS)

71
gdo vs gm in short channel

72
gdo vs gm in short channel

73
 Fliker noise
Traps at channel/oxide interface randomly
capture/release carriers
k
V (f)
g
2

fWLCox
Kf Kf
I (f)
2
d n

f f
Parameterized by Kf and n
Provided by fab (note n 1)
Currently: Kf of PMOS << Kf of NMOS due to buried channel
To minimize: want large area (high WL)

74
 Induced Gate Noise
Fluctuating channel potential couples
capacitively into the gate terminal, causing a
noise gate current
2

i 4kTdg do
2



ng
5 T
d is gate noise coefficient
Typically assumed to be 2g
Correlated to drain noise!

75
 real
Input impedance
1 g m Ldeg
Z in ( s) s ( Lg Ldeg )
sC gs C gs
Set to be real and equal to source resistance:
1 g m Ldeg

2
Rs
( Lg Ldeg )C gs
0
C gs

76
 Output noise current

I d2 ( f ) kTg g do 1 2 c d d2 (4Q2 1)
Noise scaling factor:
1
4

1 2 c d d2 (4Q 2 1) d
gm d
g do 5g
Where for 0.18 process
c=-j0.55, g=3, d=6, gdo=2gm,
d = 0.32

1 0 ( Lg Ldeg )
Q
2 Rs0C gs 2 Rs

77
 Noise factor
o g g do
F 1
1 2 c d (4Q 2 1) d2
T 2Q g m
Noise factor scaling coefficient:

g g do
K nf


2Q g m

1 2 c d (4Q 1) d
2 2

Compare:
N device G Nin g 0 g
NF 1 0 4( RsCgs ) 1
2 2
4
0
G Nin Rs g m T 2Q
78
Noise factor scaling coefficient versus Q

79
 Example
Assume Rs = 50 Ohms, Q = 2, fo = 1.8 GHz, ft = 47.8 GHz
From 1
Q
2 Rs0C gs
1 1
C gs 442 fF
2 Rs0Q 2(50)2 1.8e9(2)
Rs C gs Rs 50
Ldeg 0.17nH
gm T 2 47.8e9
1 1

2
Lg 2 Ldeg 17.5nH
( Lg Ldeg )Cgs 0 Cgs
0

80
Have We Chosen the Correct Bias Point?

IIP3 is also a function of Q

81
 If we choose Vgs=1V
Idens = 175 A/m
From Cgs = 442 fF, W=274m
Ibias = IdensW = 48 mA, too large!

Solution 1: lower Idens => lower power,

lower fT, lower IIP3
Solution 2: lower W => lower power, lower
Cgs, higher Q, higher NF

82
 Lower current density to 100

Need to verify that IIP3 still OK (once we know Q) 83

 Lower current density to 100
g m 0.78 gm d 2
0.68 d 0.68 0.43
g do 1.15 g do 5 5
g m 0.78mS
T 2 42.8 GHz
Cgs 2.9 fF
We now need to re-plot the Noise Factor scaling coefficient
- Also plot over a wider range of Q

o g do 1
F 1 g 1 2 c d (4Q 1) d
2 2

T g m 2Q

84
85
 Recall

We previously chose Q = 2, lets now choose Q = 6

- Cuts power dissipation by a factor of 3!
- New value of W is one third the old one
274 m
W 91m
3
86
 Rs = 50 Ohms, Q = 6, fo = 1.8 GHz, ft =
42.8 GHz
Ibias = IdensW =100A/m*91m=9.1mA
Power = 9.1 * 1.8 = 16.4 mW
Noise factor scaling coeff = 10
Noise factor = 1+ wo/wt * 10
= 1+ 1.8G/42.8G *10 = 1.42
Noise figure = 10*log(1.42) = 1.52 dB
Cgs=442/3=147fF
Ldeg=Rs/wt=0.19nH
Lg=1/(wo^2Cgs) Ldeg = 53 nH
87
 Other architectures of LNAs

Add output load to achieve voltage gain

In practice, use cascode to boost gain
Added benefit of removing Cgd effect

88
Differential LNA
Value of Ldeg is now much better controlled
Much less sensitivity to noise from other circuits

But: Twice the power as the single-ended version

Requires differential input at the chip

89
 LNA Employing Current Re-Use

PMOS is biased using a current mirror

NMOS current adjusted to match the PMOS current
Note: not clear how the matching network is achieving a 50 Ohm match
Perhaps parasitic bondwire inductance is degenerating the PMOS or
NMOS transistors?
90
 Combining inductive
degeneration and current reuse

Current reuse to save power

Larger area due to two degeneration

inductor if implemented on chip
NF: 2dB, Power gain: 17.5dB, IIP3: -
6dBm, Id: 8mA from 2.7V power supply

Can have differential version

F. Gatta, E. Sacchi, et al, A 2-dB Noise Figure 900MHz Differential CMOS LNA,
IEEE JSSC, Vol. 36, No. 10, Oct. 2001 pp. 1444-1452

91
 At DC, M1 and M2 are in cascode
At AC, M1 and M2 are in cascade
S of M2 is AC shorted
Gm of M1 and M2 are multiplied.
Same biasing current in M1 & M2

LIANG-HUI LI AND HUEY-RU CHUANG, MICROWAVE JOURNAL from the February 2004 issue.

92
 IM3 components in the drain
current of the main transistor has
the required information of its
nonlinearity
Auxiliary circuit is used to tune the
magnitude and phase of IM3
components
Addition of main and auxiliary
transistor currents results in
negligible IM3 components at
output
ia g m1va g v g v 2
m2 a
3
m3 a

ib g m3vb3
i o ia ib
Sivakumar Ganesan, Edgar Snchez-sinencio, And Jose Silva-martinez
IEEE Transactions On Microwave Theory And Techniques, Vol. 54, No. 12, December 2006 93
MOS in weak inversion has speed problem
MOS transistor in weak inversion acts like bipolar
Bipolar available in TSMC 0.18 technology (not a parasitic BJT)
Why not using that bipolar transistor to improve linearity ?

94
Inter-stage Inductor gain boost

Inter-stage inductor with

parasitic capacitance form
impedance match network between
input stage and cascoded stage
boost gain lower noise figure.

Input match condition will be

affected

95
 Folded cascode

Low supply voltage

Ld reduces or eliminates
Effect of Cgd1

Good fT

96
 Design Procedure for Inductive
Source Degenerated LNA
Noise factor equations:

o g do 1
F 1 g
1 2 c d (4Q 2 1) d2
T g m 2Q
g do 1

K nf g

1 2 c d (4Q 1) d
2 2

g m 2Q

97
 Targeted Specifications

Frequency 2.4 GHz ISM Band

Noise Figure 1.6 dB
IIP3 -8 dBm
Voltage gain 20 dB
Power < 10mA from 1.8V

98
 Step 1: Know your process
A 0.18um CMOS Process
Process related
tox = 4.1e-9 m
e = 3.9*(8.85e-12) F/m
= 3.274e-2 m^2/V.s
Vth = 0.52 V
Noise related
= gm/gdo
d/g ~ 2
g~3
c = -j0.55

99
Step 2: Obtain design guide plots

100
 Insights:
gdo increases all the way with current
density Iden
gm saturates when Iden larger than
120A/m
Velocity saturation, mobility degradation ----
short channel effects
Low gm/current efficiency
High linearity
deviates from long channel value (1)
with large Iden

101
Obtain design guide plots

102
 Insights:
fT increases with Vod when Vod is small and
saturates after Vod > 0.3V --- short channel
effects
Cgs/W increases slowly after Vod > 0.2V
fT begins to degrade when Vod > 0.8V
gm saturates
Cgs increases

Should keep Vod ~0.2 to 0.4 V

103
 Obtain design guide plots
knf vs input Q and current density
3-D plot for visual
inspection

2-D plots for

design reference

104
 Design trade-offs
For fixed Iden, increasing Q will reduce the
size of transistor thus reduce total power --
-- noise figure will become larger
For fixed Q, reducing Iden will reduce
power, but will increase noise factor
For large Iden, there is an optimal Q for
minimum noise factor, but power may be
too high

105
 Obtain design guide plots
Linearity plots :IIP3 vs. gate overdrive and transistor size

106
 Insights:
MOS transistor IIP3 only, when embedded into
actual circuit:
Input Q will degrade IIP3
Non-linear memory effect will degrade IIP3
Output non-linearity will degrade IIP3
IIP3 is a very weak function of device size
Generally, large overdrive means large IIP3
But the relationship between IIP3 and gate overdrive
is not monotonic
There is a local maxima around 0.1V overdrive

107
 Step 4: Estimate fT

Small current budget ( < 10mA )

does not allow large gate over drive :
Vod ~ 0.2 V ~ 0.4 V
fT ~ 40 ~ 44 GHz
108
Step 4: Determine Iden, Q and
Calculate Device Size

Gm/W~0.4

Select Iden = 70 A/m, =>Vod~0.23V

109
If Q = 4, IIP3 will have enough margin:
Estimated IIP3:
IIP3(from curve) 20log(Q) = 8-12 = -4dBm
Specs require: -8 dBm
110
Q=4 and Iden = 70A/m meet the
noise factor requirement

111
Gm=0.4*128 ~ 50 mS fT = gm/(Cgs*2pi) = 48 GHz

112
Step 6: Simulation Verification

Large deviation

113
114
Comparison between targeted
specs and simulation results

Parameter Target Simulated

Noise Figure 1.6 dB 0.8 dB
Drain Current < 10mA 8 mA
Voltage gain 20 dB 21 dB
IIP3 -8 dBm -6.4 dBm
P1dB -20dbm
S11 -17 dB
Power supply 1.8 V 1.8 V

115