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Analog and Digital VLSI Design

EEE F313/INSTR F313

Lecture 2: VLSI Design Flow & Challenges in VLSI Design

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VLSI Design Flow FAB

Front End
Layout Verification
Design Specification and Testing

Behavioral Description Physical layout

RTL Description (HDL)

Floor planning and
Automatic Place and Route

Functional Back End

Verification and
Testing Logical Verification
and Testing
Processes

Logic Synthesis Gate-level Netlist

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Challenges in Digital Design

Microscopic issues
ultra-high speeds
power dissipation and supply
rail drop
growing importance of
interconnect
noise, crosstalk
reliability, manufacturability Macroscopic issues
clock distribution time-to-market
design complexity (millions of
gates)
high levels of abstractions
design for test
reuse and IP, portability
systems on a chip (SoC)
tool interoperability
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Scaling
Technology shrinks by 0.7 times every generation

With every generation we can integrate 2x more

functionality

Cost of a function decreases by 2x

How to design chips with more and more functions ??

Need for Efficient Design Methodologies

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Design Abstraction
SYSTEM

MODULE
+

GATE

CIRCUIT

DEVICE
G
S D
n+ n+
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Next Class

Design Metrics
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Thank You