CE6306

Application Specific Integrated Circuit Design

HDL Design Flow

Xianan WANG

9/12/2017

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 Hardware Description Languages (HDL)

HDL is used to describe hardware.

Two popular languages:

VHDL

Verilog

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 HDL Design Flow

Model Digital System

In different abstraction, behavioral (high) or structural (low)

Verify Design

Test design with defined input combinations

Synthesize Circuits

Convert from abstract description into schematic design

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 Design Specification (SPEC)

entity 2_bit_full_adder is
Port (
A: in std_logic_vector (1 downto 0);
A[1:0] B: in std_logic_vector(1 downto 0);
S[1:0] Cin: in bit;
2-bit full adder S: out std_logic_vector(1 downto 0);
B[1:0] Cout: out bit);
end 2_bit_full_adder
Cin Cout

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 Behavioral Model:

Described in logic expression.

Tell synthesizer to assemble specific function.

Synthesizer decides basic units and connection

used in program.

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 Structural Model:

Described by functional units and connections

Tell synthesizer the exact circuit design.

User decides both functionality and circuit

structure.

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 A VHDL Example: Up-Down Counter

1. Counter adds(or
subtracts) 1 at
rising edge of
clock
clock
Up-Down Counter 2. When up_down = 0,
reset adds; when up_down
Counter[3:0]
= 1, subtracts
up_down 3. When reset = 1,
reset counter to
0000

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 Behavioral Model: Outline
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity up_down_counter is
port( clock: in std_logic;
reset: in std_logic;
up_down: in std_logic;
counter: out std_logic_vector(3 downto 0)
);
end up_down_counter;

architecture bhv of up_down_counter is

begin
end bhv;
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 Behavioral Model: Implementation
architecture bhv of up_down_counter is
signal t_count: std_logic_vector(3 downto 0);
Begin
process(clock, reset)
begin
if(reset = '1') then
t_count <= "0000";
elsif rising_edge(clock) then
if up_down = '0' then
t_count <= t_count + 1;
else
t_count <= t_count - 1;
end if;
end if;
end process;
counter <= t_count;
end bhv;

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 Testbench: Verify functionality

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 Testbench: Outline
library ieee;
use ieee.std_logic_1164.all;

entity tb_up_down is
end tb_up_down; // empty entity

architecture tb_arch of tb_up_down is

begin
end architecture tb_arch;

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 Testbench: Instantiate DUT
*DUT Design Under Test

architecture tb_arch of tb_up_down is

component up_down_counter
port(
clock: in std_logic;
reset: in std_logic;
up_down: in std_logic;
counter: out std_logic_vector(3 downto 0)
);
end component;

end tb_arch

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 Testbench: Map Ports
architecture tb_arch of tb_up_down is

signal clock: std_logic := '0';
signal reset: std_logic := '0';
signal up_down: std_logic := '0';

signal counter: std_logic_vector(3 downto 0);

begin
uut: up_down_counter port map (
clock => clock,
reset => reset,
up_down => up_down,
counter => counter
);

end tb_arch;

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 Testbench: Generate and Feed Input(1)
architecture tb_arch of tb_up_down is
constant clock_period: time := 20 ns;

clock_process: process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;

end tb_arch;

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 Testbench: Generate and Feed Input(2)
architecture tb_arch of tb_up_down is

stim_proc: process
begin
wait for 20 ns;
reset <= '1';
wait for 20 ns;
reset <= '0';
up_down <= '0';
wait for 200 ns;
up_down <= '1';
wait;
end process;

end tb_arch;

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 ModelSim: Create Project (1)

1. File -> New -> Project;

2. Pomp Create Project , type

in Project Name, keep
others as default;

3. Click OK to confirm.

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 ModelSim: Create Project (2)

1. Pomp Add items to the

Project window, click Add
Existing File, import your
program into project;
2. (or right click project,
select Add to Project,
import your program into
program)
3. Program includes both your
model and testbench
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 ModelSim: Compile Project
1. Press Compile All to
compile project;
2. If error detected, debug
your program;
3. If no error is detected,
project is compiled
successfully.

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 ModelSim: Simulate
1. Simulate -> Start Simulation;

2. Find your testbench entity;

3. Define resolution;

4. Press OK.

(Recommends not to select Enable

Optimization)

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 ModelSim: Simulate
1. Select all signals that you want
to observe;

2. Right click, select Add Wave.

Then signals are added to the
figure.

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 ModelSim: Simulate

1. Define simulation run length

and (or) other settings

2. Press Run

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 1. Waveform is generated;

2. Verify functionality.

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