8259A PIC- INTERRUPT OPERATION

To implement interrupt, the interrupt Enable FF must be

enabled.
8259A should be initialized by writing control words in
the control register.
8259 requires two types of control words:
ICW Used to set up proper conditions
and specify RST vector address.
OCW Used to perform functions such as
masking interrupts, setting up status
read operations etc.
After 8259A is initialized, the following sequence of
events occurs when one or more interrupt request lines
go high.
8259A PIC- INTERRUPT OPERATION

1. IRR stores the Interrupt requests.

2. Priority Resolver Checks three registers:
IRR for interrupt requests.
IMR for Masking bits.
ISR for the interrupt request being serviced.
It resolves the priority and sets the INT high
when appropriate.
3. MPU acknowledges the interrupt by sending
interrupt acknowledge.
8259A PIC- INTERRUPT OPERATION

4. After is received, the appropriate priority

bit in the ISR is set to indicate which level is
being served and the corresponding bit in the
IRR is reset to that request is accepted. Then
op-code for CALL instruction is placed on the
Data Bus.
5. When MPU decodes the CALL instruction, it
places two more signals on the data
bus.
8259A PIC- INTERRUPT OPERATION

6. When 8259 receives second , it

places lower order byte of CALL address
on the data bus.
Third High order byte.
The CALL address is the vector memory
location for the interrupt. This address is
placed in control register during
initialization.
8259A PIC- INTERRUPT OPERATION

7. During third pulse, the ISR bit is reset

either automatically (AEOI) or by a command
word that must be issued at the end of the
service routine (EOI). This option is determined
by the ICW.
8. The program sequence is transferred to the
memory location specified by the CALL
instruction.
AEOI Automatic End of Interrupt Mode
EOI End of Interrupt Mode
 8259A PIC- COMMAND WORDS
Two types: ICW, OCW
ICW:
Before start functioning, 8259 must be initialized
by writing two to four command words into their
respective command word registers.
A0=0,D4=1: The control word is ICW1. ICW1
contains the control bits for edge/level triggered
mode, single/cascade mode, call address
interval and whether ICW4 is required or not etc.
A0=1: ICW2Store details interrupt vector
addresses.
 8259A PIC- ICW1
The following initialization procedure Carried out internally
when ICW1 is loaded.
a) The edge sense circuit is reset i.e. by default 8259A
interrupts are edge sensitive.
b) IMR is cleared.
c) IR7 input is assigned lowest priority.
d) Slave mode address is set to 7.
e) Special mask mode is cleared and status read is set to
IRR.
f) If IC4=0, all functions of ICW4 are set to Zero.
Master/slave bit in ICW4 bit is used in buffered mode
only.
INITIALIZATION SEQUENCE OF 8259A

ICW1 & ICW2 are

Compulsory command
Words in the initialization
sequence.

ICW3 & ICW4 are

Optional.

ICW3 is read only when

More than one 8259 used
in the system ( SNGL bit in
ICW1 is 0).
ADI=1 for 8086 based system

For 8086 Dont Care

p
For 8085 system they are filled by A15-A11 of the interrupt vector address and
Least significant 3 bits are same as the respective bits of the vector address.
For 8086 system they are filled by most significant 5 bits of interrupt type and
the least significant 3 bits are 0, pointing to IR0.
If BUF=0,M/S is to be neglected.