Verilog Scheduling Semantics

Prepared By:
Jayesh Popat
Sonali Patel
 Event Regions
Definition:
The term simulation time is used to refer to
the time value maintained by the simulator to
model the actual time it would take for the
system description being simulated. The term
time is used interchangeably with simulation
time.
timeslot: all simulation activity that is
processed in the event regions for each
simulation time.
IEEE P1800/D4 Draft Standard for SystemVerilog - Unified Hardware Design, Specification, and
Verification Language (working draft of the SystemVerilog Standards Group).
 Race Condition
The term originates with the idea of two signals
racing each other attempting to influence the
output first
Example:-2
Example:-1 always @(posedge clk)
assign p = q; begin
initial begin x = 1'b0;
q = 1; y = x;
#1 q = 0; end
$display(p); always @(posedge clk)
End begin x = 1'b1;
*What is the value of p? end
*What is the value of y?
 Non determinism
Example:-4
module DFF (clk, q, d);
input clk, d;
output q;
reg q;
always @(posedge clk)
q = d;
endmodule
module DFF_chain;
DFF dff1(clk, q1, d1);
What is value of q2?
DFF dff2(clk, q2, q1);
endmodule
 Self triggering blocks
module osc2 (clk);
output clk;
reg clk;

initial #10 clk = 0;

always @(clk)
begin
#10 clk <= ~clk;
$display("time=%0g",$time," clk = %b",clk);
end
endmodule
Coding guidelines to avoid Race
condition in Verilog
Event Regions Verilog 2001
 Scheduling Semantics Verilog
Events at simulation time are stratified into four
layers of events in the order of processing:

Active events at the same simulation time are

processed in an arbitrary order. An example of an
active event is a blocking assignment.
 Active Events Region
Execute all module blocking assignments
Evaluate the Right-Hand-Side (RHS) of all
nonblocking assignments and schedule
updates into the NBA region.
Execute all module continuous assignments
Evaluate inputs and update outputs of Verilog
primitives.
Execute the $display and $finish commands.
 Inactive Events Region
Inactive region is where #0 blocking
assignments are scheduled.
We should not make #0 RTL procedural
assignments as per the guideline.
For good coding practices there are no need
for #0 RTL assignments and hence, the
Inactive region will be deleted from the rest of
the events.
Nonblocking Assignment Region
(NBA).
NBA region is to execute the updates to LHS
variables that were scheduled in the Active
region for all currently executing NBA.

As Race Avoidance Guideline dictates that all

RTL clocked logic modeled using an always
block should be coded using NBA to ensure
that the sequential logic will execute in the
NBA region and correctly model the pipelined
nature of sequential elements.
 Example
Bad Modeling: Good Moeling
always @(posedge clk) begin
always @(posedge clk) q1 <= d;
begin q2 <= q1;
q3 <= q2;
q1 = d; end
q2 = q1; always @(posedge clk) begin
q3 = q2; q3 <= q2;
end q2 <= q1;
q1 <= d;
end
No matter of sequence for
always @(posedge clk) Nonblocking
begin always @(posedge clk) q1<=d;
always @(posedge clk) q2<=q1;
q3 = q2; always @(posedge clk) q3<=q2;
q2 = q1; always @(posedge clk) q2<=q1;
q1 = d; always @(posedge clk) q3<=q2;
always @(posedge clk) q1<=d;
 Postponed Region
Postponed Region execute the $strobe and
$monitor commands that will show the final
updated values for the current timestep.

There is no feedback path from the Postponed

region back into the RTL or Reactive-loop
regions, so the values displayed and the
coverage collected will be the final values for
that timestep.
Example