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Kuen-Jong Lee
A 32 bit adder
A 32 bit counter
A 107-transistor CPU
A 109-transistor SOC
0 0
0
0 0 0/1
Related fields
Verification: To verify the correctness of a
design
Diagnosis: To tell the faulty site
Reliability: To tell whether a good system will work
correctly or not after some time.
Debug: To find the faulty site and try to eliminate the fault
VLSI Testing Introduction.4 NCKUEE-KJLEE
Why Studying Testing?
Economics!
Reduce test cost (enhance profit)
Automatic test equipment (ATE) is extremely
expensive
Shorten time-to-market
Market dominating or sharing
Guarantee IC quality and reliability
Defects detected in Cost
Rule of Ten: Wafer 0.01 0.1
Cost to detect faulty Packaged chip 0.1 1
IC increases by an Board 1 10
order of magnitude System 10 100
Field 100 1000
VLSI Testing Introduction.5 NCKUEE-KJLEE
Principle of Testing
Input Patterns Output Response
-1011 Circuit 1-001
11-00 under 0011-
-0-1- -1101
01--0 Test 1001-
0-101 (CUT) 01-11
Stored
Correct Comparator
Response
Test Result
Testing typically consists of
Applying set of test stimuli (input patterns, test vectors)
to inputs of circuit under test (CUT), and
Analyzing output responses
The quality of the tested circuits will depend upon
the thoroughness of the test vectors
VLSI Testing Introduction.6 NCKUEE-KJLEE
Importance of testing
N = # transistors in a chip
p = prob. (a transistor is faulty)
Pf = prob. (the chip is faulty)
Pf = 1- (1- p) N
If p = 10-6
N = 106
Pf = 63.2%
Vss
Logic simulation
Fault simulation ATPG
Test generation
C C
4 1
B
C3 C2
Gate level
A E Higher/ System level
B
G
C
D F
A E
A s-a-1 B s-a-1 C s-a-1 D s-a-1
B A s-a-0 B s-a-0 C s-a-0 D s-a-0
G
E s-a-1 F s-a-1 G s-a-1
C E s-a-0 F s-a-0 G s-a-0
D F
14 faults
Other fault models:
- Break faults, Bridging faults, Transistor stuck-open faults,
Transistor stuck-on faults, Delay faults
Faulty Chip
Defects
Wafer
Shipped Parts
IC
Testing
Fabrication
Yield: Quality:
Fraction of Defective parts
good parts per million (DPM)
Rejects
A I C
A D B C
CC
CC
IR
1
2
B F
G
B RB
F IF
E CD C
C E E
JE
H
D E
No
More faults? Exit
Yes
Select a fault
Fault
dropping
Test generation
Fault simulation
1. Reconvergent fanout
Combinational part
PIs POs
Y J
K
Y CK clk
MUX
T/N
Combinational Combinational
logic logic
SO
FF SFF
FF SFF
FF SFF
T/N
VLSI Testing Introduction.27 SI NCKUEE-KJLEE
Scan Cell Design
Q DI Q,SO
DI D Q D Q
SI
CK CK
N/T
(SE)
Q Q,SO
DI DI
F
F
SI
F FT F + FT
Most cell libraries now have scan cells!
Combinational
Circuits
Q D Q D Q D Q D
SO SI SI SI SI
SE
CLK
TRST*
TRST* TRST*
TRST* TRST*
Response
generator
Analyzer
pattern
BIST good/fail
Controller
biston bistdone
VLSI Testing Introduction.32 NCKUEE-KJLEE
Built-In-Self Test (BIST) (Cont.)
Remainder Quotient
R x x 2 x 4 1 x2
VLSI Testing Introduction.35 NCKUEE-KJLEE
Signature Analyzer (SA) (cont.)
A LFSR performs polynomial division
P x : x 5 x 4 x 2 1
Q x : x 2 1
x7 x6 x 4 x 2 x5 x 4 x 2 1
x x x 1
7 6 5
Px Qx Rx x 7 x 6 x5 x 4 x 2 1 Gx
Before After
sys_di
sys_addr data
di
sys_wen
clk
data hold_l Memory q
addr Memory
Module rst_l Module
test_h
wen si so
se
sys_addr
Pattern Generator
Algorithm-Based
di
sys_d addr Memory data
isys_wen wen
Module
rst_l
Compressor
clk q
compress_h clk
hold_l
rst
test_h si so
se
BIST Circuitry
logic
rst_l
clk
Bist Memory
hold_l
control
test_h
bist_se
compressor bist_so TDO
bist
decoder
int_scan mbist
scan
decoder
decoder
TDI
TCK IR
TAP Controller
TMS
An SOC