Signal and Timing Parameters II

Source Synchronous Timing Class 3

1
Contents
2

Synchronous Bus Limitations

Source Synchronous Concept &
Advantages
Operation
Timing Equations
Timing Loop Analysis
Maximum Transfer Rate
Beyond Double Pumping
Edge Considerations
Signal Parameters & Timing Class 3
Common Clock Limitations
3

CLK
Clock

A B
Data
f max 1 Tcycle ,min Tdriver,max T flight,max Tsetup Tskew
Tcycle,min

Max frequency is defined by min cycle time

Min cycle time is limited by maximum delays.
Can we find a way to remove the dependence on
absolute delays?

Signal Parameters & Timing Class 3

 4

Source Synchronous Signaling Concept

Strobe
A B
Data
The transmitting agent (A) sends the clock (strobe), along
with the data signal.
A central clock is not (directly) required to control data flow from
transmitter to receiver.
Overview:
Drive the strobe and data signals with a known phase relationship.
Design the strobe and data signals to be identical in order to
preserve the phase relationship.
As long as the phase relationship can be maintained, the lines can
be arbitrarily long (limited by other effects, such as losses,
latencies, etc.).
Signal Parameters & Timing Class 3
 5

Source Synchronous Concept Example

Suppose that we transmit a data signal 1 ns prior to
transmitting the strobe.
Youre given a 500 ps receiver setup requirement.
You find that the flight time for the data signal
varies between 5.5 ns and 5.7 ns.
You find that the flight time for the strobe signal
also varies between 5.5 ns and 5.7 ns, but the two
signals are not correlated.
Can we meet the setup requirement?

Signal Parameters & Timing Class 3

Source Synchronous Advantage
6

From the preceding example, it should be apparent

that source synchronous performance depends on
relative, rather than absolute delays.
True for drivers and interconnect, though we must still
meet the absolute setup/hold requirements for the
receiver.
In real systems, the difference in delay between
signals can be made much smaller than the absolute
delays.
Therefore, with source synchronous signaling we
can expect
to achieve higher performance
to be able to use longer traces

Signal Parameters & Timing Class 3

Transfer Rate Comparison
7

Source
Synchronous
Synchronous
400 MT/s
FSB 133 MHz
(533 MT/s)
266 MT/s
Graphics 66 MHz
(533 MT/s)
Memory 133 MHz 800 MT/s

Items in parentheses are in development, all others

are released in products.

Signal Parameters & Timing Class 3

Source Synchronous Bus Operation
8

Driver Chip From Core

D Q
D
DELAY
Strobe n
n

From Core
D Q

P
L
L Data

Clock Distribution
Tree

Receiver Chip Data

To Core
Q D
Q D

System
n
Clock

Strobe
P
L
L
Clock Distribution Tree

Signal Parameters & Timing Class 3

Operation #2
9
Driver Chip From Core

D Q
D

The timing path starts

DELAY
Strobe n
n
at the flip-flop of the
transmitting agent and
From Core
D Q
P

ends at the flip-flop of L

L Data

the receiving agent. Clock Distribution

Tree

The strobe signal is used Receiver Chip

To Core
Q D
Data

as the clock input of the

Q D

receiver flip-flop. System

Clock
n

Strobe
P
L
L
Clock Distribution Tree

The transmitted strobe (and data) signals are generated

from the on-chip bus clock.
Typically, the strobe is phase shifted by cycle from the
data signal. Some buses do the shifting in the receiver.
Duty cycle variations will cause variation on the phase
relationship

Signal Parameters & Timing Class 3

Operation #2
10
Driver Chip From Core

D Q
D
DELAY

Typically, there is
Strobe n
n

one strobe signal From Core

D Q

(or pair of signals)

P
L
L Data

per two bytes of Clock Distribution

Tree

data signals. Receiver Chip

To Core
Q D
Q D
Data

Varies by design System n

Signal relationships
Clock

Strobe
at the transmitter P

are shown below.

L
L
Clock Distribution Tree

CLK

DATA

Setup Hold Setup Hold

STROBE

Signal Parameters & Timing Class 3

 Source Synchronous Operation
11

@ RECEIVER
Truman Tsu Th Thmar
STROBE/STROBE
Tsuskew Thskew

Tvb Tva
@ DRIVER

DATA

Tsuskew: flight time skew for setup Thskew: flight time skew for hold
Tsumar: setup margin Thmar: hold margin
Tvb: min driver phase offset (setup) Tvb: min driver phase offset (hold)
Signal Parameters & Timing Class 3
Source Synchronous Equations
12

@ RECEIVER
Truman Tsu Th Thmar
STROBE/STROBE
Tsuskew Thskew

Tvb Tva
@ DRIVER

DATA

The sum of the timings at the receiver must equal the

timing at the driver:
Tvb Tsu Tsuskew Tsumar Tva Th Thskew Thmar
This implies that we must design with minimum driver
offsets:
Tvb Tsu Tsuskew Tva Th Thskew
Signal Parameters & Timing Class 3
Source Synchronous Equations #2
13

@ RECEIVER
Truman Tsu Th Thmar
STROBE/STROBE
Tsuskew Thskew

Tvb Tva
@ DRIVER

DATA

We must also satisfy the following relationship:

Tcycle ,min Tva Tvb
This determines our maximum transfer rate.
f max 1
Tcycle,min

Signal Parameters & Timing Class 3

Question
14

Based on what weve covered in the previous

slides, what are the implications to:
The transmitter design?
The receiver design?
The interconnect design?
Example:
Tsu = 500 ps, Th = 250 ps
The target transfer rate is 500 MT/s.
What are reasonable flight time skew targets?

Signal Parameters & Timing Class 3

 15

Setup Timing Diagram & Loop Analysis

TBCLK

BCLK
TBCLK/4

DCLK
Tco(STB)

DRIVER STB/STB
Tco(DATA)
Tflight(STB)

DRIVER DATA

RECEIVER STB/STB
Tflight(DATA) Tsu

RECEIVER DATA Tsumar

Tco STB T flight STB Tsu Tsumar Tco DATA T flight DATA 0
TBCLK
4
Signal Parameters & Timing Class 3
 16

Setup Analysis
Tco STB T flight STB Tsu Tsumar Tco DATA T flight DATA 0
TBCLK
4
For a double pumped bus, the difference between Tco(DATA)
and Tco(STB) is typically set to one-half of the cycle time
(TDCLK/2 = TBCLK/4) to center the strobe in the data valid
window.
Double pumped: source synchronous transfer rate is 2x the
central clock rate.
This relationship is typically specified as Tvb (data valid
before strobe ), which signifies the minimum time for which
the data at the transmitter is valid prior to transmission of the
strobe.
Mathematically: T T DATA T STB BCLK
T
vb , min co co max 4
Simplify the loop equation:
Tvb ,min T flight STB Tsu Tsumar T flight DATA 0

Signal Parameters & Timing Class 3

Setup Analysis #2
17

Tvb,min Tsu T flight STB T flight DATA Tsumar

Both data & strobe propagate over the interconnect.

Goal: identical flight times.
In reality, there will be some difference in flight
times between data and strobe.
trace length, loading, crosstalk, ISI, etc.
Define flight time skew for the setup condition:
Tsuskew T flight DATA T flight STB max

Simplify the loop equation:

Tvb ,min Tsu Tsuskew Tsumar

Signal Parameters & Timing Class 3

Notes on the Setup Equation
18

Tvb,min Tsu Tsuskew Tsumar

You may see the timing equation
written in other forms.
The way we defined Tvb makes it a
negative quantity. Others may define
it to be positive.
We defined Tsuskew to be a positive
quantity.

Signal Parameters & Timing Class 3

 19

Hold Timing Diagram & Loop Analysis

TBCLK

BCLK
TBCLK/4

DCLK
Tco(STB) Tco(DATA)

DRIVER STB/STB
Tflight(STB)

DRIVER DATA

RECEIVER STB/STB Tflight(DATA) T

h
Thma
r

RECEIVER DATA

Tco DATA T flight DATA Thmar Thold T flight STB Tco STB 0
TBCLK
4
Signal Parameters & Timing Class 3
Hold Analysis
20

Tco DATA T flight DATA Thmar Thold T flight STB Tco STB 0
TBCLK
4
Just as for the setup case, we need to specify the
minimum phase relationship between data and
strobe: Tva ,min Tco DATA Tco STB TBCLK
min 4
In addition, define the flight time skew for the
hold case:
Thskew T flightDATA T flightSTB min

In addition, define the flight time skew for the

hold case: T
va , min Thold Thskew Thmar

Note that the Thskew is defined such that it is a

negative quantity, while Tva is defined to be
positive.
Signal Parameters & Timing Class 3
Maximum Transfer Rate
21

-Tvb,min Tva,min

STB/STB

DATA

Tcycle,min

The maximum transfer rate can be

determined using the definitions for Tva
and Tvb. T 4T T DATA T STB
BCLK va , min co co min

T 4 T T DATA T STB
BCLK vb , min co co max

We can calculate the limit of TBCLK (for a

double pumped bus) by adding the two
equations above.
TBCLK ,min 4 Tvb ,min Tva ,min
Signal Parameters & Timing Class 3
 Higher Transfer Rates (e.g. Quad Pumped) 22

TBCLK TBCLK

BCLK BCLK
TBCLK/8 TBCLK/8

DCLK DCLK
Tco(STB) Tco(STB) Tco(DATA)
DRIVER STB/STB DRIVER STB/STB
Tco(DATA) Tflight(STB) Tflight(STB)

DRIVER DATA DRIVER DATA

RECEIVER STB/STB Tflight(DATA) Thold

RECEIVER STB/STB
Tflight(DATA) Tsetup Tmargin
RECEIVER DATA RECEIVER DATA
Tmargin

The setup and hold equations remain the same.

What changes are the Tva and Tvb definitions:

Tvb Tco DATA Tco STB max

TBCLK
8
Tva Tco DATA Tco STB min
TBCLK
8
Signal Parameters & Timing Class 3
 23

Part C: Edge Considerations and Real Specs

Signal Parameters & Timing Class 3

 Review Edge Triggered Clocking
24

Data in Data
(d) out (Q)

D-Latch

clock
(clk)

Data in
(d)
Clock to out time or
data valid time

clock
(clk)
Hold
time
Data
out (Q)

Set up time

Signal Parameters & Timing Class 3

Finer look at the latch
25

Data in
First stage is a
buffer Internal output
Converts to internal Threshold
digital levels Buffer delay
Its convenient to
think of buffer as time

differential Threshold
comparator Data in Internal output

Signal Parameters & Timing Class 3

Switching Threshold
26

The transfer function of the Linear

input buffer is linear for Region
only for a very small region
on a input signals edge.
We want it to work in the
saturation region above and Saturated
below threshold. Region
This is so the output is either is
high or low and converted to the
internal voltage representation of
high or low. I.e. binary SI engineers often
measure slew rate
The assumption is that the signal as a reported
edge is sufficiently fast enough to budget parameter
guarantee predictable switching of
high to low and visa-versa.

Signal Parameters & Timing Class 3

Vil and Vih
27

Data in
Vil is the voltage
required to switch the Vih
output of the input
buffer to a low state. Vil

Vih is the voltage

required to switch the
output of the input
buffer to a high state.

Signal Parameters & Timing Class 3

Relation to timing
28

Transmitter out out into

reference load
Transmitter output times are
measured at a threshold level.
This is how the Tcos are
measured.
Max and min values reported in Output Reference Threshold
budgets are normally
The maximum of all the design
configuration and process
variations max values
The minimum of all the design
configurations and process Input to Receiver
variations min values.
Min low going edge Flight time Vih
Max high going edge Flight time

Min high going edge Flight time

Max low going edge Flight time Vil

Signal Parameters & Timing Class 3

 29

Assignment: Determine Tva and Tvb

Give UI (unit interval =
10 ns)
Meaning 20ns period and
10ns bit time with
sufficiently fast rise
time
The sources are 1 Volt
with source resistance
of 50 ohms
Data has 5pF tied to it
Strobe has 10p tied to
it.
The threshold voltage
VOL and VOH are 0.8 v
What are Tva and Tvb

Signal Parameters & Timing Class 3