Sunday, July 30, 2017 Mahdi Hassanpour

Contents:
Introduction
Block Diagram and Pin Description of the 8051
Registers
Memory mapping in 8051
Stack in the 8051
I/O Port Programming
Timer
Interrupt

Sunday, July 30, 2017 Mahdi Hassanpour

 Why do we need to learn
Microprocessors/controllers?
The microprocessor is the core of
computer systems.
Nowadays many communication, digital
entertainment, portable devices, are
controlled by them.
A designer should know what types of
components he needs, ways to reduce
production costs and product reliable.

Sunday, July 30, 2017 Mahdi Hassanpour

 Different aspects of a
microprocessor/controller

Hardware :Interface to the real world

Software :order how to deal with inputs

Sunday, July 30, 2017 Mahdi Hassanpour

 The necessary tools for a
microprocessor/controller
CPU: Central Processing Unit
I/O: Input /Output
Bus: Address bus & Data bus
Memory: RAM & ROM
Timer
Interrupt
Serial Port
Parallel Port
Sunday, July 30, 2017 Mahdi Hassanpour
 Microprocessors:
General-purpose microprocessor
CPU for Computers
No RAM, ROM, I/O on CPU chip itself
ExampleIntels x86, Motorolas 680x0

Many chips on mothers board

Data Bus
CPU
General-
Serial
Purpose RAM ROM I/O Timer COM
Micro- Port
Port
processor
Address Bus

General-Purpose Microprocessor System

Sunday, July 30, 2017 Mahdi Hassanpour

 Microcontroller :
A smaller computer
On-chip RAM, ROM, I/O ports...
ExampleMotorolas 6811, Intels 8051, Zilogs Z8 and PIC 16X

CPU RAM ROM

A single chip
Serial
I/O Timer COM
Port
Port
Microcontroller

Sunday, July 30, 2017 Mahdi Hassanpour

 Microprocessor vs. Microcontroller
Microprocessor
CPU is stand-alone, RAM,
ROM, I/O, timer are separate
designer can decide on the
amount of ROM, RAM and
I/O ports.
expansive
versatility
general-purpose
Sunday, July 30, 2017 Mahdi Hassanpour
Microcontroller
CPU, RAM, ROM, I/O and
timer are all on a single chip
fix amount of on-chip ROM,
RAM, I/O ports
for applications in which cost,
power and space are critical
single-purpose
 Embedded System

Embedded system means the processor is embedded into that

application.
An embedded product uses a microprocessor or microcontroller to do
one task only.
In an embedded system, there is only one application software that is
typically burned into ROM.
Exampleprinter, keyboard, video game player

Sunday, July 30, 2017 Mahdi Hassanpour

 Three criteria in Choosing a Microcontroller

1. meeting the computing needs of the task efficiently and cost

effectively
speed, the amount of ROM and RAM, the number of I/O ports
and timers, size, packaging, power consumption
easy to upgrade
cost per unit
2. availability of software development tools
assemblers, debuggers, C compilers, emulator, simulator,
technical support
3. wide availability and reliable sources of the microcontrollers.

Sunday, July 30, 2017 Mahdi Hassanpour

 Block Diagram
External interrupts
On-chip Timer/Counter

Interrupt ROM for

On-chip Timer 1 Counter
Control program
code RAM Timer 0 Inputs

CPU

Bus Serial
4 I/O Ports
OSC Control Port

P0 P1 P2 P3 TxD RxD
Address/Data

Sunday, July 30, 2017 Mahdi Hassanpour

Sunday, July 30, 2017 Mahdi Hassanpour
 Pin Description of the 8051
P1.0 1 40 Vcc
P1.1 2 39 P0.0(AD0)
P1.2 3 38 P0.1(AD1)
P1.3
P1.4
4
5
8051 37
36
P0.2(AD2)
P0.3(AD3)
P1.5 6 (8031) 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
(RXD)P3.0 10 31 EA/VPP
(TXD)P3.1 11 30 ALE/PROG
(INT0)P3.2 12 29 PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)

Sunday, July 30, 2017 Mahdi Hassanpour

 Pins of 80511/4

Vccpin 40
Vcc provides supply voltage to the chip.
The voltage source is +5V.
GNDpin 20ground
XTAL1 and XTAL2pins 19,18

Sunday, July 30, 2017 Mahdi Hassanpour

 Figure (a). XTAL Connection to 8051

Using a quartz crystal oscillator

We can observe the frequency on the XTAL2 pin.

C2
XTAL2
30pF

C1
XTAL1
30pF

GND

Sunday, July 30, 2017 Mahdi Hassanpour

 Pins of 80512/4

RSTpin 9reset
It is an input pin and is active highnormally low.
The high pulse must be high at least 2 machine cycles.
It is a power-on reset.
Upon applying a high pulse to RST, the
microcontroller will reset and all values in registers
will be lost.
Reset values of some 8051 registers

Sunday, July 30, 2017 Mahdi Hassanpour

 Figure (b). Power-On RESET Circuit
Vcc

10 uF 31
EA/VPP
30 pF X1
19
11.0592 MHz
8.2 K
X2
18
30 pF
9 RST

Sunday, July 30, 2017 Mahdi Hassanpour

 Pins of 80513/4

/EApin 31external access

There is no on-chip ROM in 8031 and 8032 .
The /EA pin is connected to GND to indicate the code is
stored externally.
/PSEN ALE are used for external ROM.
For 8051, /EA pin is connected to Vcc.
/ means active low.
/PSENpin 29program store enable
This is an output pin and is connected to the OE pin of the
ROM.

Sunday, July 30, 2017 Mahdi Hassanpour

 Pins of 80514/4

ALEpin 30address latch enable

It is an output pin and is active high.
8051 port 0 provides both address and data.
The ALE pin is used for de-multiplexing the address
and data by connecting to the G pin of the 74LS373
latch.
I/O port pins
The four ports P0, P1, P2, and P3.
Each port uses 8 pins.
All I/O pins are bi-directional.

Sunday, July 30, 2017 Mahdi Hassanpour

 Pins of I/O Port

The 8051 has four I/O ports

Port 0 pins 32-39P0P0.0P0.7
Port 1pins 1-8 P1P1.0P1.7
Port 2pins 21-28P2P2.0P2.7
Port 3pins 10-17P3P3.0P3.7
Each port has 8 pins.
Named P0.X X=0,1,...,7, P1.X, P2.X, P3.X
ExP0.0 is the bit 0LSBof P0
ExP0.7 is the bit 7MSBof P0
These 8 bits form a byte.
Each port can be used as input or output (bi-direction).

Sunday, July 30, 2017 Mahdi Hassanpour

 Hardware Structure of I/O Pin
Each pin of I/O ports
Internal CPU buscommunicate with CPU
A D latch store the value of this pin
D latch is controlled by Write to latch
Write to latch1write data into the D latch
2 Tri-state buffer
TB1: controlled by Read pin
Read pin1really read the data present at the pin
TB2: controlled by Read latch
Read latch1read value from internal latch
A transistor M1 gate
Gate=0: open
Gate=1: close
Sunday, July 30, 2017 Mahdi Hassanpour
 D Latch:

Sunday, July 30, 2017 Mahdi Hassanpour

 A Pin of Port 1

Read latch Vcc

TB2
Load(L1)

Internal CPU D Q P1.X

bus P1.X pin

Write to latch Clk Q M1

TB1
Read pin P0.x
8051 IC
Sunday, July 30, 2017 Mahdi Hassanpour
 Writing 1 to Output Pin P1.X

Read latch Vcc

TB2
Load(L1) 2. output pin is
1. write a 1 to the pin Vcc
D Q
1 P1.X
Internal CPU
bus P1.X pin
0 output 1
Write to latch Clk Q M1

TB1
Read pin

8051 IC
Sunday, July 30, 2017 Mahdi Hassanpour
 Writing 0 to Output Pin P1.X

Read latch Vcc

TB2
Load(L1) 2. output pin is
1. write a 0 to the pin ground
D Q
0 P1.X
Internal CPU
bus P1.X pin
1 output 0
Write to latch Clk Q M1

TB1
Read pin

8051 IC
Sunday, July 30, 2017 Mahdi Hassanpour
 Reading High at Input Pin

Read latch Vcc 2. MOV A,P1

TB2 external pin=High
1. write a 1 to the pin MOV Load(L1)
P1,#0FFH

1 1 P1.X pin
Internal CPU bus D Q
P1.X
0 M1
Write to latch Clk Q

TB1
Read pin
3. Read pin=1 Read latch=0
Write to latch=1
8051 IC

Sunday, July 30, 2017 Mahdi Hassanpour

 Reading Low at Input Pin

Read latch Vcc 2. MOV A,P1

TB2
1. write a 1 to the pin Load(L1) external pin=Low
MOV P1,#0FFH
1 0 P1.X pin
Internal CPU bus D Q
P1.X
0 M1
Write to latch Clk Q

TB1
Read pin
3. Read pin=1 Read latch=0
Write to latch=1
8051 IC

Sunday, July 30, 2017 Mahdi Hassanpour

 Other Pins
P1, P2, and P3 have internal pull-up resisters.
P1, P2, and P3 are not open drain.
P0 has no internal pull-up resistors and does not
connects to Vcc inside the 8051.
P0 is open drain.
Compare the figures of P1.X and P0.X.
However, for a programmer, it is the same to program
P0, P1, P2 and P3.
All the ports upon RESET are configured as output.

Sunday, July 30, 2017 Mahdi Hassanpour

 A Pin of Port 0

Read latch
TB2

Internal CPU D Q P0.X

bus P1.X pin

Write to latch Clk Q M1

TB1
Read pin P1.x

8051 IC
Sunday, July 30, 2017 Mahdi Hassanpour
 Port 0 with Pull-Up Resistors

Vcc
10 K

P0.0

Port
DS5000 P0.1
P0.2
8751 P0.3
8951 P0.4 0
P0.5
P0.6
P0.7

Sunday, July 30, 2017 Mahdi Hassanpour

 Port 3 Alternate Functions
P3 Bit Function Pin

P3.0 RxD 10
P3.1 TxD 11
P3.2 INT0 12
P3.3 INT1 13
P3.4 T0 14
P3.5 T1 15
P3.6 WR 16
P3.7 RD 17

Sunday, July 30, 2017 Mahdi Hassanpour

 RESET Value of Some 8051 Registers:

Register Reset Value

PC 0000
ACC 0000
B 0000
PSW 0000
SP 0007
DPTR 0000
RAM are all zero.

Sunday, July 30, 2017 Mahdi Hassanpour
 Registers
A

R0
DPTR DPH DPL
R1

R2 PC PC
R3

R4 Some 8051 16-bit Register

R5

R6

R7

Some 8-bitt Registers of

the 8051

Sunday, July 30, 2017 Mahdi Hassanpour

 Memory mapping in 8051

ROM memory map in 8051 family

4k 8k 32k
0000H 0000H 0000H

0FFFH
DS5000-32

1FFFH
8751
AT89C51
8752
AT89C52 7FFFH

from Atmel Corporation

from Dallas Semiconductor

Sunday, July 30, 2017 Mahdi Hassanpour

 RAM memory space allocation in the 8051

7FH

Scratch pad RAM

30H

2FH
Bit-Addressable RAM

20H
1FH Register Bank 3
18H
17H
Register Bank 2
10H
0FH (Stack) Register Bank 1
08H
07H
Register Bank 0
00H

Sunday, July 30, 2017 Mahdi Hassanpour

 Stack in the 8051
The register used to access 7FH
the stack is called SP (stack
Scratch pad RAM
pointer) register.
30H

The stack pointer in the 8051 2FH

Bit-Addressable RAM
is only 8 bits wide, which
20H
means that it can take value 1FH Register Bank 3
00 to FFH. When 8051 18H
17H
powered up, the SP register 10H
Register Bank 2

contains value 07. 0FH (Stack) Register Bank 1

08H
07H
Register Bank 0
00H

Sunday, July 30, 2017 Mahdi Hassanpour

 Timer :

Sunday, July 30, 2017 Mahdi Hassanpour

Sunday, July 30, 2017 Mahdi Hassanpour
 TMOD Register:

Gate : When set, timer only runs while INT(0,1) is

high.
C/T : Counter/Timer select bit.
M1 : Mode bit 1.
M0 : Mode bit 0.

Sunday, July 30, 2017 Mahdi Hassanpour

 TCON Register:

TF1: Timer 1 overflow flag.

TR1: Timer 1 run control bit.
TF0: Timer 0 overflag.
TR0: Timer 0 run control bit.
IE1: External interrupt 1 edge flag.
IT1: External interrupt 1 type flag.
IE0: External interrupt 0 edge flag.
IT0: External interrupt 0 type flag.

Sunday, July 30, 2017 Mahdi Hassanpour

 Interrupt :

Sunday, July 30, 2017 Mahdi Hassanpour

Interrupt Enable Register :

EA : Global enable/disable.
--- : Undefined.
ET2 :Enable Timer 2 interrupt.
ES :Enable Serial port interrupt.
ET1 :Enable Timer 1 interrupt.
EX1 :Enable External 1 interrupt.
ET0 : Enable Timer 0 interrupt.
EX0 : Enable External 0 interrupt.

Sunday, July 30, 2017 Mahdi Hassanpour