ECE260B

ECE260B
CSE241A
Winter 2005
Power Distribution
Website: http://vlsicad.ucsd.edu/courses/ece260b-w05
ECE 260B CSE 241A Power Distribution 1 http://vlsicad.ucsd.edu

Motivation
Power supply noise is a serious issue in DSM design

Noise is getting worse as technology scales
Noise margin decreases as supply voltage scales
Power supply noise may slow down circuit performance
Power supply noise may cause logic failures

Power =
Vcc
Routing resources
Vss
20-40% of all metal tracks used by Vcc, Vss
Increased power denser power grid Vcc
Pins Vss
Vcc or Vss pin carries 0.5-1W of power
Pentium 4 uses 423 pins; 223 Vcc or Vss Vcc
More pins package more expensive
(+ package development, motherboard redesign, )
Battery cost
1kg NiCad battery powers a Pentium 4 alone for less than 1 hour
Performance
High chip temperatures degrade circuit performance
Large across-chip temperature variations induce clock skew
High chip power limits use of high-performance circuits
Power transients determine minimum power supply voltage
Power = Package
Pentium 4 die is about 1.5g and less than 1cm^3
Pentium-4 in package with interposer, heat sink, and fan can be 500g and 150cm^3
Fan
Heat Sink Processor
Integrated Processor
Heat Spreader Pins
Decoupling OLGA Pins

Capacitors
Interposer Package Pins
Modern processor packaging is complex and adds significantly to product cost.

http://www.intel.com/support/processors/procid/ptype.htm
Courtesy M. McDermott UT-Austin

Planning for Power
Early simulation of major power dissipation components
Early quantification of chip power
- Total chip power
- Maximum power density
- Total chip power fluctuations
inherent & added fluctuations due to clock gating
Early power distribution analysis (dc, ac, & multi-cycle)

I.e., average, maximum, multi-cycle fluctuations
Early allocation & coordination of chip resources

- Wiring tracks for power grid
- Low Vt devices
- Dynamic circuits
- Clock gating
- Placement and quantity of added decoupling capacitors
Power and Ground Routing
Floorplanning includes planning how the power, ground

and clock should route
Power supply distribution
Tree: trunk must supply current to all branches
Resistance must be very small since when a gate switches, its
current flows through the supply lines
- If the resistance of supply lines is too large, voltage supplied to
gates will drop, which can cause the gate to malfunction
- Usually, want at most 5-10% IR drop due to supply resistance
Usually on the top layers of metal, then distributed to lower
wiring layers

Planar Power Distribution
Topology of VDD/VSS networks.

Inter-digitated
VSS
Design each macrocell such that all VDD and VSS VDD
terminals are on opposite sides.
If floorplan places all macrocells with VDD on same cell
side, then no crossing between VDD and VSS. VSS
VDD
cut line
VDD
VSS
B
VDD
VDD VSS
no cut line
C
VDD cut line
VSS A
VSS VDD
VDD
VSS VSS
no connection
Courtesy K. Yang, UCLA

Gridded Power Distribution
With more metal layers, power is striped
Connection between the stripes allows a power grid
- Minimizes series resistance
Connection of lower layer layout/cells to the grid is through vias
- Note that planar supply routing is often still needed for a strong
lower layer connection.
- There may not be sufficient area to make a strong connection in the
middle of a design (connect better at periphery of die)

Power Supply Drop/Noise
Supply noise = variations in power supply voltage that act as noise source for logic gates
Power supply wiring resistance voltage variations with current surges
Current surges depend on dynamic behavior of circuit
Solution approach
Measure maximum current required by each block
Redesign power/ground network to reduce resistance
Worst case: move activity to another clock cycle to reduce peak current scheduling problem
Example: Drive 32-bit bus, total bus wire load = 2pF, with delay 0.5ns
R for each transistor needs to be < 0.25k to meet RC = 0.5ns
Effective R of bits together is 250/32 = 7.5
For < 10% drop, power distribution R must be < 1

Electromigration
Physical migration of metal atoms due to electron wind can
eventually create a break in a wire
MTTF (mean time to failure) 1/J2 where J= current density
Current density must not exceed specification wire Ii/wi < Jspec
Specified as mA per m wire width (e.g., 1mA/ m) or mA per via cut
EM occurs both in signal (AC=bidirectional) and power wires (DC =

unidirectional)
Much worse for DC than AC; DC occurs inside cells and in power buses
May need more contacts on transistor sources and drains to meet

EM limits
Width of power buses must support both iR and EM requirements
Issues in IR and EM constraint generation
Topology is most likely not a tree
How do we determine current patterns?
Effects of R, L
What Happens?
Example of an AlCu line seen under

microscope.
Accelerated by higher temperature
and high currents
Voids form on grain boundaries
Metal atoms move with current away
from voids and collect at boundaries
Catastrophic
failure

Taken from http://www.nd.edu/~micro/fig20.html
Taken from Sverre Sjthun, Electromigration

In-Depth, from www.dpwg.com
Courtesy S. Sapatnekar, UMinn

Power Supply Rules of Thumb
Rules depend on technology

Tech file has rules for resistance and electromigration
Examples:
Must have a contact for each 16 of transistor width (more is
better)
Wire must have less than 1mA/m of width
Power/Gnd width = Length of wire * Sum (all transistors
connected to wire) / 3*106 (very approximate)
For small designs, power supply design is non-issue

Basic Methodology Concepts
Reliability (slotting, splitting)

Alignment of hierarchical rings, stripes
Isolation of analog power
Styles of power distribution
Rings and trunks
Uniform grid
Bottom-up grid generation
Depends on:
- Package: flip-chip vs. wire-bond; I/O count (fewer pads denser grid)
- Power budget
- IR drop limits
- Floorplan constraints (hard macros, etc.)

Metal Slotting vs. Splitting
Required by metal layout Easy connections

through standard via
rules for uniform CMP arrays
(planarization) GND
Split power wires GND
Less data than traditional GND
slotting GND
More accurate R/C

M1 M1
analysis of power mesh
Not supported by all tools
Difficult to connect -
where should vias go?
Courtesy Cadence Design Systems, Inc.

Trunks and Rings Methodology
Each Block has its own ring

Rings may be inside the blocks or part of the top level
Each Block has trunks connecting top level to block
G V G V
Rings may be shared with
abutted blocks block 3 Individual trunks
V
V
block connecting
G
5 blocks to top level
G
block 2
V
block
4
G
V
block
V
G
1
G V G V G V

Trunks and Rings
Advantages Disadvantages
Power tailored to the demands Limited redundancy, power grid
of each block (flexible) built to match needs
Assumptions in design may

More area efficient since the change or be invalid
demands of each block are
uniquely met Non regular structure requires
more detailed IR drop/EM
Simple implementation analysis
supported by many tools
missing vias/connections fatal
Rings can be shared between
blocks by abutted blocks Rings will require
slotting/splitting due to wide
widths
Increase in data volume

Uniform Chip Grid Methodology
Robust and redundant power

network
mainly in microprocessors and high end
global grid Fine or custom grid
large ASICs
higher layers or no grid
on lower layers
Implementation G V G V
Primary distribution through upper metal
layers
V
V
block 5 block 4
- Lower layers in blocks to connect to top
G
through via stacks
G
block 3
Typically pushed into blocks
V
block 4
V
Blocks typically abut
- Requires block grids to align block 1
V
Rows/Followpins should align with block
pins
- Global buffer insertion G V G V G V

Uniform Chip Grid
Advantages
Disadvantages
Easily implemented
Takes up significant routing
Lends itself to straightforward hand resources (20%-40% of all
calculations
routing tracks if not already
reserved for power/ground)
Path redundancy allows less Fine grids may slow down P&R
sensitively to changes in current tools
pattern
Imposes grid structure into each
Mesh of power/ground provides block which may be unnecessary
shielding (for capacitance) and
current returns (for inductance) Top and blocks coupled closely if
top level routing pushed into
Top-down propagation easy to use blocks
on this style Changes to block/top must be
reflected in other

Bottom-Up Grid Generation Methodology
Design and optimize power grid for block, merge at top

Advantages
Able to tailor grid for routing resource
efficiency in each block
Flexibility to choose the best grid for
the block (i.e. ring and stripe, power
plane, grid)
Disadvantages
Designing grid in context of the big picture is more difficult
Block grid may present challenging connections to top level
Assumptions for block grids connection to top level must be analyzed
and validated
Power Routing in Area-Based P&R
Power routing approaches
(1) Pre-route parts of power grid during floorplanning
(2) Build grid (except connections to standard cells) before P&R
(3) Build entire grid before P&R
N.B.: Area-based P&R tools respect pre-routes absolutely
Cadence tools: power routing done inside SE, all other

tasks (clock, place, route, scan, ) done by point tools
Lab 5 tomorrow has a tiny bit of power routing (rings, stripes)
Miscellany
ECOs: What happens to rings and trunks if blocks change size?
Layer choices: What is cost of skipping layers (to get from thick
top-layer metal down to finer layers)?
How wide should power wires be?
Post-processing strategies
Power Routing Wire Width Considerations
Slotting rules: Choose maximum width below slotting width

Halation (width-dependent spacing) rules: Do as much as
possible of power routing below wide wire width to save routing
space
Choose power routing widths carefully to avoid blocking extra
tracks (and, use the space if blocking the track!)
What is better power width here? Blocked tracks

Power Routing Tool Usage
4 layer power grid example (HVHV)

Turn on via stacking
Route metal2 vertically
Route metal4 vertically (use same coordinates)
Route metal3 horizontally (make coincident with every N metal1
routes)
Turn off via stacking
Route metal1 horizontally
metal2/metal4
coincident metal1 inside cells
metal3 every n micron

Post-Processing Flows (DEF or Layout Editing)
During PnR After post processing

(Tree) Supply Network Design
Tree topology assumption not very useful in practice, but

illustrates some basic ideas
Assume R dominates, L and C negligible
marginally permissible assumption
Current drawn at various points in

the tree (time-varying waveform)
Supply
Current causes a V=IR drop
Ground is not at 0V
Vdd is not at intended level
= sinks
IR Drop Constraints
Chowdhury and Breuer, TCAD 7/88

Can write V drop to each sink as Supply
Ri Ii < Vspec
for all sink current patterns made available
Tree structure: can compute Ii easily
Ri li / w i
Change wi to reduce IR drop

Objective: minimize ai wi
Current density must never exceed a specification
For each wire, Ii/wi < Jspec

P/G Mesh Optimization (R only)
Dutta and Marek-Sadowska, DAC 89

Cost function: ai li wi = ai cili2 // = total wire area
(since ci = conductance = wi/( li)
Constraints
- EM: Ii e wi // current density I/w less than upper bound
Substitute Ii = vi (wi/ li) // I = V/R
vp - vq e li // divide by wi, * li
- Wire width constraints: Wmin wi Wmax (translate to ci)
- Voltage drop constraints: va - vb Vspec1 and/or vi Vspec2
- Circuit equations that determine the vs
Variables: cis (vis depend on cis)

Solution Technique
Method of feasible directions

Find an initial feasible solution (satisfies all constraints)
Choose a direction that maintains feasibility
Make a move in that direction to reduce cost function
Given a set of cis, must find corresponding vis

Feasible direction method: move from point c* to c+
c* and c+ must be close to each other (i.e., if you have the
solution at c*, the solution at c+ corresponds to a minor change
in conductances)
Solving for vis : solving a system of linear equations
- Solution at c* is a good guess for the solution at c+
- Converges in a few iterations

Modeling Gate Currents
Currents in supply grid caused by charging/discharging of
capacitances by logic gates
All analyses require generation of a worst-case switching
scenario
Enumeration is infeasible Two basic approaches
Simulation based methods: designer supplies hot vectors, or we
try to generate these hot vectors automatically
Pattern-independent methods: try to estimate the worst-case (can
be expensive, very inaccurate)
Once current patterns are available, apply them to supply

network to find out if constraints are satisfied

Complexity of Hot Vector Generation
Devadas et al., TCAD 3/92:

Assume zero gate delays for simplicity
Find the maximum current drawn by a block of gates
Using a current model for each gate
- Find a set of input patterns so that the total current is maximized
- Boolean assignment problem: equivalent to Weighted Max-
Satisfiability
Given a Boolean formula in conjunctive normal form (product
of sums), is there an assignment of truth values to the
variables such that the formula evaluates to True?
- Checking for Satisfiability (for k-sat, k > 2) is NP-complete
Difficult even under zero gate delay assumption

Pattern-Independent Methods
iMAX approach: Kriplani et al., TCAD 8/95

Current model for a single gate
Ipeak
Delay
Gates switch at different times

Total current drawn from Vdd (ignoring supply network C) is the
sum of these time-shifted waveforms
Objective: find the worst-case waveform

Example
(Not to scale!)
Maximum current not just a sum of individual maximum

currents
Temporal dependencies
[Using deliberate clock skews can reduce the peak
current, as we saw in the Useful-Skew discussion]
Maximum Envelope Current (MEC)
Find the time interval during which a gate may switch

Manufacturing process variations can cause changes
Actual switching event can cause changes
(unit gate delays)
Switching at second gate can occur at t=1 or at t=2

In general, a large number of paths can go through a gate;
assume (conservatively) that switching occurs in t [1,2]
Assume that all gate inputs can switch independently provides
an upper bound on the switching current

(Large) Errors in MEC Approach
G1
Correlation Problem
Switching at G0, G1, G2 and G3 not
independent G0 G2
G0 = 0 implies that G1, G2, G3 switch; G0 =
1 means that other inputs will determine gate
activity G3
If the other inputs cannot make the gate
switch in the same time window, then iMAX
estimates are pessimistic
Reconvergent Fanout Problem

G1
Signals that diverge at G0 reconverge at Gk
inputs to Gk are not independent
Assumption of independent switching is not G2 Gk
valid G0
Many heuristic refinements proposed, but

guardbanding (error) of power estimation G3
still a huge issue
Outline
Motivation
Power Supply Noise Estimation
Decoupling Capacitance (decap) Budget
Allocation of Decoupling Capacitance
Experiment Results
Conclusion

Why Decoupling Capacitance
Frequency point of view

Decaps form low-pass filters
They cancel anti- effects
Physical point of view

Decaps serve as charge reservoirs
They shortcut supply current paths and reduces voltage drop
No effect to DC supply currents

Power Supply NetworkRLC Mesh
VDD
:Current Rp
Source
Lp
: VDD pin
VDD
VDD
VDD
Slide courtesy of S Zhao, K Roy & C.-K. Kok
Current Distribution in Power Supply Mesh Illustration
Current Current flowing

:Connection point,
contribution path
VDD (1)
(3)
:VDD pin (5)
VDD
(2)
(6)
Module A B C

Current Distribution in Power Supply Network
Distribute switching current for each module in the

power supply mesh
Observation: Currents tend to flow along the least-
impedance paths
Approximation: Consider only those paths with minimal
impedance --shortest, second shortest,
I1 I 2 I n I
Z1 I 1 Z 2 I 2 Z n I n
Yj
Ij I, j 1,2, n
n
Yi
i 1

Current Flowing Paths and Power Supply
Noise Calculation
Power supply noise at a target
module is the voltage difference
between the VDD pin and the
module
Apply KVL:
i3(t)
VDD
R2 L2
R1 L1 C1 k
di j
i1(t)

(k )
C2
V (i j RP LP )
i2(t) noise
Pj T ( k )
jk jk
dt

Why Decoupling Capacitance?
i3(t)
VDD
R2 L2
R1 L1 C1 k
i1(t) C2
i2(t)
P/G network wiresizing wont Decoupling caps act as a low-pass

change voltage drop frequency filter
spectrum
Efficient to remove high frequency
To reduce Vdrop by k times needs elements of Vdrop
to size up wires by k times along
the supply current path
Decoupling Capacitance Budget
Decap budget for each module can be determined based on its noise
level
Initial budget can be estimated as follows:

Ch arg e : Q (k )
I ( k ) (t )dt
0
(k )
Noise ratio : max(1, V (lim)

noise
)
V noise
1
C ( k ) (1 )Q ( k ) /V noise , k 1,2, M
(lim)
Decap :

Iterations are performed if necessary until noise at each module in

the floorplan is kept under certain limit

Allocation of Decoupling Capacitance
Decap needs to be placed in the vicinity of each target

module
Decap requires WS to manufacture on
Use MOS capacitors
Decap allocation is reduced to WS allocation

Two-phase approach:
Allocate the existing WS in the floorplan
Insert additional WS into the floorplan if required

Allocation of Existing White Space
w2 B
A
D
WS
C
w1
E w3

Allocation of Existing WS--Linear Programming
(LP) Approach
Objective: Maximize the LP Approach:

utilization of available WS
H
Existing WS can be allocated to
max imize S xk( j ) ,
neighboring modules using LP
k 1 jN k
Notation:
S: sum of allocated WS
s.t. k Sk ,
x ( j)
jN k
k 1, 2 ,, H
Sk : area of WSk k H
S ( j) : decap budget of mod j k
x ( j)
k 1
S ( j)
, j 1, 2,, M
xk( j ) : ws allocated to mod j from WS k
N k : neighbors set of WSk xk( j ) 0, j, k
Insert Additional WS into Floorplan If
Necessary
Update decap budget for each module after existing WS
has been allocated
If additional WS if required, insert WS into floorplan by
extending it horizontally and vertically
Two-phase procedure:
insert WS band between rows based the decap budgets of the
modules in the row
insert WS band between columns based on the decap budgets
of the modules in the column

Moving Modules to Insert WS
Original floorplan Moving modules in y+ direction

0
ExtY
A B
WS
A 1 1 B
band
C D
2 C 2 D
3 F F
E 3 E
4 G G
(a) (b)

Experimental Results
Comparison of Decap Budgets
(Ours vs Greedy Solution)
Circuit decap budget decap budget Percentage

(nF) (nF) (%)
(our method) (greedy solution)
apte 27.73 32.64 85.04
xerox 8.00 13.50 59.30
hp 3.45 6.18 55.80
ami33 0 0.80 0.00
ami49 10.28 24.80 41.50
playout 42.91 61.67 69.6

Experimental Results for MCNC Benchmark
Circuits
Circuit Modules Existing decap Inacc. Added Est. Peak Est. Peak
WS Budget WS WS Noise Noise
(m2) (nF) (m2) (m2) (V) (V)
(%) (%) (%) before after
apte 9 751652 27.73 0 (0) 4794329 1.95 0.24
(1.6) (10.3)
xerox 10 1071740 8.00 0 (0) 528892 0.94 0.20

(5.5) (2.7)
hp 11 695016 3.45 306076 300824 1.09 0.23

(7.8) (3.5) (3.4)
ami33 33 244728 0 N/A 0 0.16 0.16

(21.3)
ami49 49 2484496 10.28 891672 463615 1.45 0.25

(7.0) (2.5) (1.3)
playout 62 5837072 42.91 792110 3537392 1.23 0.24
(6.6) (0.9) (4.0)

Floorplan of playout Before/After WS Insertion

Conclusion
A methodology for decoupling capacitance allocation at

floorplan level is proposed
Linear programming technique is used to allocate
existing WS to maximize its utilization
A heuristic is proposed for additional WS insertion
Compared with Greedy solution, our method produces
significantly smaller decap budgets


ECE260B - CSE241A Winter 2005 Power Distribution: Website: Http://vlsicad - Ucsd.edu/courses/ece260b-W05

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ECE 260B CSE 241A Power Distribution 1 http://vlsicad.ucsd.edu

Power supply noise is a serious issue in DSM design

ECE 260B CSE 241A Power Distribution 2 http://vlsicad.ucsd.edu

Pentium 4 die is about 1.5g and less than 1cm^3

Heat Sink Processor

Decoupling OLGA Pins

Modern processor packaging is complex and adds significantly to product cost.

Courtesy M. McDermott UT-Austin

Early power distribution analysis (dc, ac, & multi-cycle)

Early allocation & coordination of chip resources

Floorplanning includes planning how the power, ground

ECE 260B CSE 241A Power Distribution 6 http://vlsicad.ucsd.edu

Topology of VDD/VSS networks.

Courtesy K. Yang, UCLA

Courtesy K. Yang, UCLA

Courtesy K. Yang, UCLA

EM occurs both in signal (AC=bidirectional) and power wires (DC =

May need more contacts on transistor sources and drains to meet

Example of an AlCu line seen under

Courtesy K. Yang, UCLA

Taken from Sverre Sjthun, Electromigration

Courtesy S. Sapatnekar, UMinn

Rules depend on technology

For small designs, power supply design is non-issue

Courtesy K. Yang, UCLA

Reliability (slotting, splitting)

ECE 260B CSE 241A Power Distribution 14 http://vlsicad.ucsd.edu

Required by metal layout Easy connections

Split power wires GND

Less data than traditional GND

More accurate R/C

Courtesy Cadence Design Systems, Inc.

Each Block has its own ring

Each Block has trunks connecting top level to block

5 blocks to top level

Courtesy Cadence Design Systems, Inc.

Courtesy Cadence Design Systems, Inc.

Robust and redundant power

Courtesy Cadence Design Systems, Inc.

Courtesy Cadence Design Systems, Inc.

Design and optimize power grid for block, merge at top

Cadence tools: power routing done inside SE, all other

Slotting rules: Choose maximum width below slotting width

What is better power width here? Blocked tracks

Courtesy Cadence Design Systems, Inc.

4 layer power grid example (HVHV)

metal3 every n micron

Courtesy Cadence Design Systems, Inc.

During PnR After post processing

Courtesy Cadence Design Systems, Inc.

Tree topology assumption not very useful in practice, but

Current drawn at various points in

Chowdhury and Breuer, TCAD 7/88

Change wi to reduce IR drop

Courtesy S. Sapatnekar, UMinn

Dutta and Marek-Sadowska, DAC 89

Variables: cis (vis depend on cis)

Method of feasible directions

Given a set of cis, must find corresponding vis

Courtesy S. Sapatnekar, UMinn

Once current patterns are available, apply them to supply

Courtesy S. Sapatnekar, UMinn