Introductionto

MicroelectronicFabrication
by
RichardC.Jaeger
DistinguishedUniversityProfessor
ECEDepartment

AuburnUniversity
Chapter9
MOSProcessIntegration

2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. For the exclusive use of adopters of the book
This material is protected under all copyright laws as they currently exist. No Introduction to Microelectronic Fabrication, Second
portion of this material may be reproduced, in any form or by any means, Edition by Richard C. Jaeger. ISBN0-201-44494-
without permission in writing from the publisher. 1.
CopyrightNotice

2002 Pearson Education, Inc., Upper Saddle River, NJ. All

rights reserved. This material is protected under all copyright
laws as they currently exist. No portion of this material may be
reproduced, in any form or by any means, without permission in
writing from the publisher.

For the exclusive use of adopters of the book Introduction to

Microelectronic Fabrication, Second Edition by Richard C.
Jaeger. ISBN0-201-44494-1.

2002Pearson Forthe
NMOSTransistors
StructureandModel

W
V
ID = K n' V GS VTN DS V DS K n' = n CO = n OX
L 2 XO
VGS > VTN VTN = thresholdvoltage
Figure9.1

2002Pearson
Forthe
NMOSTransistors
ThresholdVoltage
EG 2K SoqN B (2 F + VSB ) Qtot
VTN = M + F +
2q CO CO

EG 2K SoqN B (2 F + VSB ) Qtot

VTP = M F
2q CO CO

kT ?N B ?
F = ln? ?
q ?n i ?

M = metal semiconductorworkfunction
= electronaffinity
M = 0.11Vforaluminumgates
M = 0Vforann + polysilicongate
M = +1.12V(E G )forap + polysilicongate
Q tot = totaloxidecharge
Figure9.2
Thresholdvoltagevs.substatedoping

2002Pearson Forthe
NMOSTransistors
ThresholdAdjustmentImplantation
Thresholdadjustmentimplants
provideadditionalvariablethat
allowsthresholdvoltagetobe
designedindependentlyfrom
substratedoping
qQi x i
VTN = 1 forx
i << x d
CO 2x d
qN B
xd =
4K So F

Figure9.5
StepapproximationtoaGaussianimpurityprofileusedtoestimate
thethresholdvoltageshiftachievedusingionimplantation

2002Pearson Forthe
NMOSTransistors
DepletionModeDevices

Figure9.6

Thresholdadjustmentimplantcancreatebuiltinchannelconnectingsource
anddraintherebycreatingNMOSdepletionmodedevice(V TN0)
Depletionmodedevicessignificantlyenhancetheperformanceof
NMOSlogiccircuitsandanalogcircuits

2002Pearson Forthe
NMOSTransistors
JunctionBreakdown
Substratedopingmustbeselected
tosupportrequireddrainsubstrate
voltage
Lightdopingincreasesbreakdown
voltage
Cylindricalandsphericalcurvatures
reducethebreakdownvoltage

2002Pearson Forthe
NMOSTransistors
DepletionLayerWidths
NMOStransistorsare
selfisolating
However,depletionlayer
widthslimitminimum
deviceseparation
Lightdopingreduces
junctioncapacitances
Figure9.4
Depletionlayerwidthofaonesidedstepjunctionasa
functionofdopingandappliedvoltage

2002Pearson Forthe
NMOSTransistors
ShallowTrenchIsolation
Depletionlayersfrom
adjacentdevicesmustnot
merge

Shallowtrenchisolation
reducesseparation
requiredbetweendevices

Figure9.7
IsolationTechniques(a)Intrinsic(b)Shallowtrench

2002Pearson Forthe
NMOSTransistors
LightlyDopedDrains(LDD)

Figure9.8
Selfalignedpolysilicongatetransistorwithlightlydopedsource/drainregions

Heavydopingindrainnearedgeofchannelreduces
breakdownvoltageofthedeviceandreducesreliability
LDDstructurereducedraindopingatedgeofchannel

2002Pearson Forthe
MOSTransistorScaling
ConstantElectricFieldScaling
Dimensionsandvoltagesreducedbyscalefactor

n OX W
2
ID = (VGS VTN )
2 X O L
W

V V 2
I
ID* = n OX GS TN = D
2 X O L

2002Pearson Forthe
MOSTransistorLayout
AlignmentErrors
Levelsmustoverlapby
atleastonealignment
tolerancetoensure
coverageandproper
deviceoperation
Figureshowsvarious
possiblemisalignments
Figure9.9 betweentwolevels

2002Pearson Forthe
MOSTransistorLayout
MaskSequence
OneAlignmentSequence
1.Source/Drainfirstmasklevel
2.Thinoxidealigntofirstlevel
3.Contactsaligntofirstlevel
4.Metalaligntolevel2

Figure9.10

2002Pearson Forthe
MOSTransistorLayout
BasedDesignRules
Designrulesforpreviousalignment
sequence

MinimumFeatureSizeF=2

AlignmentToleranceT=

Figure9.11

2002Pearson Forthe
MOSTransistorLayout
ClassicalMetalGateTransistor
Metalgatetransistorlayout
withW/L=5/1usingdesign
rulesfromFig.9.11

Totalareais4162

Channelareais202(<5%)

Figure9.12

2002Pearson Forthe
MOSTransistorLayout
SelfAlignedPolysiliconGateTransistor
Polysilicongatetransistor
layoutwithW/L=5/1using
designrulesfromFig.9.11

Totalareais1682

Channelareais202(12%)
A=1682

Figure9.13

2002Pearson Forthe
MOSTransistorLayout
MoreAggressiveLayout
Polysilicongatetransistor
layoutwithW/L=5/1using
moreaggressivedesignrules

Totalareais1202

Channelareais202(17%)

A=1202

Figure9.14

2002Pearson Forthe
MOSTransistorLayout
ChannelLength&WidthBiases
Lateraldiffusionof
source/drainregions
reduceslengthofactual
channelbelowthat
definedatthemasklevel
Lmask=2
Lactual=

Figure9.15
Similareffectoccursin
thewidthdirection

2002Pearson Forthe
CMOSTechnology
ProcessOptions

2002Pearson Forthe
CMOSTechnology
Isolation

0.13m
0.33m
3x1017/cm3

5x1016/cm3

Figure9.17Minimumspacingrequiredtoensureisolationinann
wellCMOSprocess
FromEx.9.4inthebook,theminimumspacingis
0.33m+0.33m+0.13m=0.79m
Useaspacingof1mtoincludeasafetymargin

2002Pearson Forthe
CMOSTechnology
Latchup
Thefourlayerpnpn
structureusedinCMOScan
operateasanSCRifthebias
conditionsareright
IftheSCRistriggeredinto
conduction,thelatchup
condition,thendestructive
currentscanoccur
Mustbeavoidedbyproper
biasinganddevicedesign

2002Pearson Forthe
CMOSTechnology
ShallowTrenchIsolation
Shallowtrench
isolationinatwin
wellprocess
Interceptsdepletion
layerspermitting
tighterspacing
Reducesthechance
oflatchup

2002Pearson Forthe
CMOSTechnology
SilicononInsulator(SOI)
Twowaferscanbebonded
togethertoformsiliconon
insulatormaterial

Deepoxygenimplantation
canbeusedtocreatea
buriedoxidelayer
(SIMOX)

2002Pearson Forthe
CMOSTechnology
SilicononInsulator(SOI)

Figure9.20TrenchisolatedSOI
Silicononinsulator

2002Pearson Forthe
MOSProcessIntegration
References

2002Pearson Forthe
 EndofChapter9

2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. For the exclusive use of adopters of the book
This material is protected under all copyright laws as they currently exist. No Introduction to Microelectronic Fabrication, Second
portion of this material may be reproduced, in any form or by any means, Edition by Richard C. Jaeger. ISBN0-201-44494-
without permission in writing from the publisher. 1.