Design Issues in VLSI

Implementations
Dr. R.K. Sharma
Professor

ECE Department
NIT Kurukshetra

Email: mail2drrks@gmail.com Mob. : 09896688346

TECHNOLOGY CHOICES FOR DIGITAL
CIRCUIT DESIGN
Technology Timeline
Comparisons of different types of signal
processing units
DESIGN LANGUAGES
Overview of a General-Purpose Processor
FSM : Moore vs Mealy
Design for Simple
Computation

Prof.(Dr.) R.K.Sharma, ECED, NIT Kurukshetra

Controller and Data Path

Prof.(Dr.) R.K.Sharma, ECED, NIT Kurukshetra

Controller State Diagram

Prof.(Dr.) R.K.Sharma, ECED, NIT Kurukshetra

Complete Circuit of the Basic Processor
 Power Distribution in
Microprocessor

APRIL 4,2009
 Truism in VLSI
Everyone is always looking for
BIGGER FUNCTIONALITY
SMALLER SIZE
FASTER
RELIABLE

LOW POWER
LOW COST
PORTABLE
 DESIGN CONSTRAINTS ?

Power Consumption
 Problems of Power Dissipation

Continuously increasing
performance demands
Increasing power dissipation of
technical devices
Today: power dissipation is a
main problem
High Power dissipation leads to:

Reduced
Reducedtime
timeof
ofoperation
operation High
Highefforts
effortsfor
forcooling
cooling
Higher
Higherweight
weight(batteries)
(batteries) Increasing
Increasingoperational
operationalcosts
costs
Reduced
Reducedmobility
mobility Reduced
Reducedreliability
reliability
IMPACT of HEAT
 CO2 Emission
Combustion of Fossil Fuels, for electricity generation,
transportation, and heating, and also the manufacture of cement,
all result in the total worldwide emission of about 22 billion tons
of carbon dioxide to the atmosphere each year. About a third of
this comes from electricity generation, and another third from
transportation, and a third from all other sources.

CO2 comes mainly from the burning of coal, oil and other fossil
fuels to generate electricity and contributes about 50% to the
greenhouse effect.

Consumer Electronics ( Information, Communication,

Entertainment sector ) use electricity that is created mainly from
burning coal. Every time we switch on a light we are adding to
 Global Warming ?
Global Warming is the increase of Earth's average
surface temperature due to effect of greenhouse
gases, such as carbon dioxide emissions from
burning fossil fuels or from deforestation, which
trap heat that would otherwise escape from Earth.

This is a type of

GREENHOUSE EFFECT.
 Low power
Economic aspect
A massive 3bn worth of electricity is currently spent
powering consumer electronic and computer products
alone in the UK every year - that's 30% of the
average household electricity bill.

UKs Energy Saving Trust claimed that consumer

electronics could account for 45 per cent of home
electricity demand by 2020. So energy efficient
technologies can help protect the global climate.
 Components of Power

PTotal = P Switching
+ P Short-Circuit
+ P Glitches
+ P Leakage
 Sources of Power Consumption and
Remedies
Reduce the active load:
Technology scaling:
Minimize the circuits
The highest win
Use more efficient Thresholds should scale
design Leakage starts to byte
Charge recycling Dynamic voltage scaling
More efficient layout

Psw = k CL V 2
DD f
CLK

Reduce Switching Run it slower:

Activity: Use parallelism
Conditional clock Less pipeline
Conditional precharge stages
Switching-off inactive Use double-edge
blocks flip-flop
Conditional execution
Short Circuit Power
Short Circuit Power
 Transition Timings
for Inputs and Outputs

Prof.(Dr.) R.K.Sharma,
ECED, NIT Kurukshetra
Glitch at the Output

Prof.(Dr.) R.K.Sharma,
ECED, NIT Kurukshetra
 Glitching Power
Dissipation:
Glitches occur due to a mismatch or imbalance
in the path lengths in the logic network

As a result in a multi-level logic circuits a node

can exhibit multiple transitions in a single clock
cycle before settling to the correct logic level.

These intermediate erroneous outputs lead to a

power loss.
Prof.(Dr.) R.K.Sharma,
ECED, NIT Kurukshetra
 Condition for No Glitch

Where:

Prof.(Dr.) R.K.Sharma,
ECED, NIT Kurukshetra
Glitch Elimination by Hazard
Filtering

Prof.(Dr.) R.K.Sharma,
ECED, NIT Kurukshetra
Glitch Elimination by Path
Delay Balancing

Prof.(Dr.) R.K.Sharma,
ECED, NIT Kurukshetra
 Leakage current mechanism

I1: Reverse Bias pn Junction Leakage; I2 :

Subthreshold Leakage

I3: Oxide Tunneling Current; I4: Hot Carrier

Injection
 Subthreshold Current

APRIL 4,2009
 State-of-the-art design techniques to reduce power:
User-reported popularity of power management
techniques.

Power-management techniques survey from 115

respondents from SoC designers in wireless
communication(31%), portable electronics(21%), and
networking(27%).
 Power Gating with Sleep
Transistors

APRIL 4,2009
 Time Displace Outputs
of NAND and NOR

APRIL 4,2009
 Truth Table of Full Adder

APRIL 4,2009
 Full Adder Cell

APRIL 4,2009
DVFS
DVFS
 Choices for Power Reduction

. .
 Opportunities for power
reduction

80% of power reduction opportunities are till RTL

Early attention to power consumption is necessary for maximum
power savings.
APRIL 4,2009
Setup Time Constraint
Hold Time Constraint
What is Skew ?
Setup Time Constraint
 Double Clocking ?

However, when the skew is

excessively negative, the
signal may arrive so early
that it races through
capturing flip-flop resulting in
double clocking or a Hold-
Time violation.
 Clock Skew ?
Clock Skew is caused by unbalanced
delays in clock distribution networks
This can be attributed to:
Uneven wire lengths along clock
paths.
Mismatches in the number of buffers
along clock paths.
Differences in clock load driven by
clock buffers.
Clock Period Variations ?

Time-varying variations in the

operating conditions of a
circuit cause temporal
variation of the clock period
at a given point on the chip-
called Clock Jitter
JITTER
 Switching Activities
Cause Jitter
All variations, listed in previous slide, are
due to Switching activities , which may
vary from cycle to cycle.
Switching activities cause variations in:

Interconnect Couplings
Gate Capacitances
Voltages of internal nodes of latches
and FFs
Noise Created on Parasitic
Components Due to
Switching