Topics

Memories:
ROM;
SRAM;
DRAM;
Flash.
Image sensors.
FPGAs.
PLAs.
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
 High-density memory
architecture

Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf

 Memory operation

Address is divided into row, column.

Row may contain full word or more than one
word.
Selected row drives/senses bit lines in
columns.
Amplifiers/drivers read/write bit lines.

Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf

 Read-only memory (ROM)

ROM core is organized as NOR gates

pulldown transistors of NOR determine
programming.
Erasable ROMs require special processing
that is not typically available.
ROMs on digital ICs are generally mask-
programmedplacement of pulldowns
determines ROM contents.
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
 ROM core circuit

Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf

 Static RAM (SRAM)

Core cell uses six-transistor circuit to store

value.
Value is stored symmetricallyboth true
and complement are stored on cross-
coupled transistors.
SRAM retains value as long as power is
applied to circuit.

Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf

 SRAM core cell

Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf

 SRAM core operation

Read:
precharge bit and bit high;
set select line high from row decoder;
one bit line will be pulled down.
Write:
set bit/bit to desired (complementary) values;
set select line high;
drive on bit lines will flip state if necessary.

Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf

 SRAM sense amp

Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf

 Sense amp operation

Differential pairtakes advantage of

complementarity of bit lines.
When one bit line goes low, that arm of diff
pair reduces its current, causing
compensating increase in current in other
arm.
Sense amp can be cross-coupled to increase
speed.
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
 3-transistor dynamic RAM
(DRAM)
First form of DRAMmodern commercial
DRAMs use one-transistor cell.
3-transistor cell can easily be made with a
digital process.
Dynamic RAM loses value due to charge
leakagemust be refreshed.

Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf

 3-T DRAM core cell

Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf

 3-T DRAM operation

Value is stored on gate capacitance of t 1.

Read:
read = 1, write = 0, read_data is precharged;
t1 will pull down read_data if 1 is stored.
Write:
read = 0, write = 1, write_data = value;
guard transistor writes value onto gate
capacitance.

Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf

 3-T DRAM operation

Value is stored on gate capacitance of t 1.

Read:
read = 1, write = 0, read_data is precharged;
t1 will pull down read_data if 1 is stored.
Write:
read = 0, write = 1, write_data = value;
guard transistor writes value onto gate
capacitance.

Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf

 1-T DRAM
Word line controls
pass transistor.
Pass transistor guards
access to capacitor.
Read is destructive.

Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf

 Stacked capacitor DRAM

Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf

 Trench capacitor DRAM

Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf

 Floating gate transistor
Poly 1 gate is not
connected.
Schematic symbol: poly 2 SiO2
poly 1

n+ n+
p

Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf

 Fowler-Nordheim tunneling

+
20 V
poly 2 SiO2
poly 1
floating
p+ n+ n+ - - n+
p

n-well
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
 Fowler-Nordheim erasing

poly 2 SiO2
20 V +
-poly -1
floating floating
p+ n+ n+ n+
p

n-well
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
 NOR flash architecture
Same as NOR ROM +
but with floating gate
pullup
pulldowns.

Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf

 NAND flash architecture
Want to provide
data
banked memory for
higher data data 1 data 2
throughput. bank bank bank bank
0 1 2 3
Widely used for data
storage. address 21
Likely to become address
standard architecture.

Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf

 2-bit NAND flash cell
bit

Select top

RA0

RA1

Select bottom

Modern VLSI Design 4e: Chapter 6 n+ source Copyright 2008 Wayne Wolf
 NAND flash cell programming
bit +7V
+20V
Select top Row not
programmed
+20V
RA0
+5V
RA1
0V
Select bottom

Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf

 Wear in flash memory

Write cycles slowly damage devices.

Limited number of write cycles: 10,000.
Software balances utilization of locations to
level wear across the device.

Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf

 Image sensors

Two major types of image sensors:

Charge-coupled device (CCD) requires
specialized fabrication steps.
CMOS image sensor uses standard CMOS
technology, perhaps with low-noise
modifications.
CMOS image sensor is an array circuit
similar to a RAM.
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
 Photodiodes
Photodiode turns
photons into electrons. n
x1
Photocurrent density:
x2
p
+ x3
photons

Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf

 Active pixel sensor (APS) circuit

Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf

 APS column

Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf

 SRAM-based FPGAs

Program logic functions, interconnect using

SRAM.
Advantages:
dynamically reconfigurable;
uses standard processes.
Disadvantages:
SRAM burns power.
Possible to steal, disrupt configuration bits.

Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf

 Logic elements

Logic element includes combinational

function + register(s).
Use SRAM as lookup table for
combinational function.

Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf

 LUT-based logic element

inputs

Lookup
table out
configuration
bits

Can multiplex at output or address at input

Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
 Example
111

1, 1, 1, 0,
0, 1, 1, 0,
1, 0,
1, 10 0 1

Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf

 Evaluation of SRAM-based LUT

N-input LUT can handle function of 2n

inputs.
All logic functions take the same amount of
space.
SRAM is larger than static gate equivalent
of function.
Burns power at idle.

Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf

 Static CMOS gate vs. LUT

Number of transistors:
NAND/NOR gate has 2n transistors.
4-input LUT has 128 transistors in SRAM, 96 in multiplexer.
Delay:
4-input NAND gate has 9 delay.
SRAM decoding has 21 delay.
Power:
Static gates power depends on activity.
SRAM always burns power.

Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf

 Registers in logic elements

Want to selectively add register to LE:

Configuration bit

Comb
LE out
logic D Q

Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf

 Other LE features

Multiple logic functions in an LE.

Addition logic:
carry chain.

Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf

 Programmable interconnect

MOS switch controlled by configuration bit:

D Q

Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf

 Programmable vs. fixed
interconnect
Switch adds delay.
Transistor off-state is worse in advanced
technologies.
FPGA interconnect has extra length = added
capacitance.

Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf

 Programmable logic array (PLA)

Used to implement specialized logic

functions.
A PLA decodes only some addresses (input
values); a ROM decodes all addresses.
PLA not as common in CMOS as in nMOS,
but is used for some logic functions.

Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf

 PLA organization

p1

p2
AND plane p3 OR plane

p4

product term
i0 i0 i1 i1 f0 f1
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
 PLA structure

AND plane, OR plane, inverters together

form complete two-level logic functions.
Both AND and OR planes are implemented
as NOR circuits.
Pulldown transistors form
programming/personality of PLA. Transistors
may be referred to as programming tabs.

Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf

 PLA AND/OR cell

input 1 input 2
programming
output 1 tab

output 2
no tab
VSS

Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf