ES ZG512

Embedded System Design

Unified Modelling
Language
BITS Pilani
Pilani Campus

Surabhi Narayanan
Bangalore Professional Development Center

Outline
Introduction to UML
UML Diagrams:
State diagram
Sequence diagram
Use-case diagram
Class diagram
Activity diagram

Introduction to memory
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Introduction
UML consists of a number of graphical elements
that combine to form diagrams.
OMG (Object Management Group) Standard
The purpose of the UML diagrams is to present
multiple views of a system; this set of multiple
views is called a MODEL.
The UML model of a system tells WHAT the
system is supposed to do, NOT how to
implement the system.
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UML: Models, Views and

Diagrams

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UML Diagrams To Be
Discussed
State diagrams
Sequence diagrams
Use Case diagrams
Class diagrams
Activity diagrams
There are more, but these are used more frequently
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UML Object
The most fundamental primitives of UML are
the object and the class.
An object is an instance of a class.
Fig: An Object in UML
notation

d1 is an instance of class Display. The Display class

defines the pixels attribute seen in the object
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UML Class
A class is a form of type definitionall objects derived
from the same class have the same characteristics,
although their attributes may have different values.
A class also defines the operations that determine how
the object interacts with the rest of the world.
A class defines
both
the
interface for a
particular
type
of object and
that
objects
implementation.

Fig: A Class in UML

notation

The UML description of the Display

class
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Pilani Campus

State diagram

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State Machine
A state machine for an operation of the display is shown:
The start and stop states are special states that help us to organize the flow of the
state machine.
In some cases, we take conditional transitions out of states based on inputs or the
results of some computation done in the state. In other cases, we make an
unconditional transition to the next state.

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State Machine Example: ATM

The customer must
pass
authentication
before
withdrawing
money.
Authentication is done
by checking a PIN.

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State Machine Example: ATM

The customer must
pass
authentication
before
withdrawing
money.
Authentication is done
by checking a PIN.
The PIN can be correct
or not.

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State Machine Example: ATM

The customer must
pass
authentication
before
withdrawing
money.
Authentication is done
by checking a PIN.
The PIN can be correct
or not.
Unsuccessful attempts
are counted.

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State Machine Example: ATM

The customer must
pass
authentication
before
withdrawing
money.
Authentication is done
by checking a PIN.
The PIN can be correct
or not.
Unsuccessful attempts
are counted.
If the counter exceeds
a limit, the customer is
rejected.
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State Machine Example: ATM

The customer must
pass
authentication
before
withdrawing
money.
Authentication is done
by checking a PIN.
The PIN can be correct
or not.
Unsuccessful attempts
are counted.
If the counter exceeds
a limit, the customer is
rejected.
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State Machine Example: ATM

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Sequence diagram

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Sequence Diagram
Processing includes three objects shown at the top of the
diagram.
Extending below each object is its lifeline, a dashed line
that shows how long the object is alive.
The display object uses call events to invoke the menu
object twice: once to determine which menu item was
selected and again to actually execute the menu call.

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Sequence Diagram
Example: ATM
Flow of Events
User inserts card
System prompts user to enter
PIN
User enters PIN
System prompts user to select
services
User selects service - withdraw
money
System prompts user to enter
withdrawal amount
User enters withdrawal amount
System displays withdrawal
successful message, ejects card
and dispenses money
User collects card and money
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Sequence Diagram
Example

A customer (user) depositing money into MyAccount which is an

instance of Class SavingsAccount.
Then MyAccount object Validates the account by asking the Bank
object, MyBank to ValidateAccount.
Finally, the Customer Asks the ATM object for a Receipt by calling
the ATMs operation GetReceipt.

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Use-Case diagram

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Use-Case diagrams
A use-case diagram is a set of use-cases
A use case is a model of the interaction
between
External users of a software product (actors) and
The software product itself
More precisely, an actor is a user playing a specific
role

A use case describes what a system (or a

subsystem, class, or interface) does but it does
not specify how it does it.
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Use-Case diagrams

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Use-case Relationships
Use case

Actor

<<include>>
Use case

Other use case

<<extends>>
Use case

Use case

Other use case

Other use case

Association: Use-case is connected by

solid lines to actors that communicate
with it.
Includes: The insertion of additional
behaviour into a base use case that
explicitly describes the insertion
Extends: The insertion of additional
behaviour into a base use case that
does not know about it.
Generalization: A relationship between
a general use case and a more specific
use case that inherits and adds
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Use Case Example

PurchaseTicket
Passenger

PurchaseSingleTicket PurchaseMultipleTickets
<<includes>>

<<includes>>

CollectMoney
<<extends>>
NoChange

<<extends>>
Timeout

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Class diagram

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Links and Association

There are several types of relationships that can exist between
objects and classes:
Association occurs between objects that communicate with
each other but have no ownership relationship between them.

Fig: Associations between classes

Symbol

Meaning

Exactly one

0..1

Zero or one

M..N

From M to N

Fig: Multiplicity 0..*

From zero to any positive

integer

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Association
HR Manager
-Name: string
+ID: int
+GetName(): string
+SetName(string
sName)

HR Manager
-Name: string
+ID: int
+GetName(): string
+SetName(string
sName)

Finance
Manager

-Name: string
+ID: int
+GetName(): string
+SetName(string
sName)

R&D
Manager

-Name: string
+ID: int
+GetName(): string
+SetName(string
sName)

Binary Association (Both

Classes Know About Each
Other)
Indicated by a straight line.

Unary Association (Only

One Class Know About the
Other, Other Doesnt)
Indicated by an arrow
starting from the class that
has knowledge about the
other class and pointing
to
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Inheritance
Employee
-Name: string
+ID: int
+GetName(): string
+SetName(string
sName)

Inheritance
The child class inherits the
properties and operations of the
base class
Adds its own specific
functionalities as well

Engineer
-Name: string
+ID: int
+GetName(): string
+SetName(string
sName)

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BITS Pilani, Pilani Campus

Activity diagram

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Activity Diagram
Activity Diagram represents the workflow
It contains activity states. An activity state
represents the execution of a statement in a
procedure or the performance of an activity in a
workflow.
An activity diagram may contain branches, as well
as forking of control into concurrent threads.
Concurrent threads represent activities that can be
performed concurrently by different objects or
persons.
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Process
Order

Activity Diagram

Initial node shows where the

activity begins.
Aforkhas
oneincoming
activity
flowand
severaloutgoing concurrent
flows.
In
theProcess
Orderexample,Fill
Order,Send
Invoice,
and
their
subsequent
actions
occurin parallel.
Ajoinhas a singleoutgoing
flowwhich can proceed only
when all of theincoming
flowsreach the join.
Conditional behavior is
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Memory

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Different Classes of
Memory
Traditional Distinction between Memories:
ROM (Read Only Memory) Non-volatile
RAM (Random Access Memory) Volatile

ROMS used to get programmed once at the

beginning using a special programming units.
But at present, EEPROM and Flash memories can
be rewritten without any special programming
units.
At present following types of Memories are widely
Volatile
Nonused
SRAM
Volatile
EEPROM
Flash

DRAM

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Non-Volatile Memory
Erasing is slower than RAMs
Each device can be rewritten 1000,000 1,000,000 times only.
EEPROMs are usually used for storing non-volatile programs
and parameters.
Flash memory is usually used for storing both application
programs (including operating system) and large data records.
These are slower to read compared to RAM
It is a common practice in many real-time systems to load the
application-program (including the operating system) from a
flash memory to the RAM and then run it from the RAM.
In many cases the flash memory used is a movable one (e.g. a
SD Card or a USB Memory stick)

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SRAM and DRAM

SRAM-type memory cell requires typically 6 transistors,
while DRAM cell requires a single transistor and a capacitor
only.
So SRAM takes mores chip area compared to DRAM.
Hence SRAMs are costlier than DRAMs.
But SRAMs are faster than DRAMs.
DRAM has the issue of leakage in their storage capacitors.
So DRAMs need to be refreshed periodically (typical refresh
cycle is 3-4 ms).
While designing a RAM subsystem of a real-time system,
the basic rule of thumb is that if you need a large amount
of memory, then use DRAM, otherwise go for SRAM.
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Evolution of DRAM
First page mode (FPM) DRAM
Extended data output (EDO) DRAM
Synchronous DRAM (SDRAM)
Direct Rambus DRAM (DRDRAM)
Double data rate 3 synchronous DRAM (DDR3
DRAM)

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Memory Hierarchy
CPU Clock Rates are increasing at a faster rate
compared to DRAM access times.
Programmers always desire faster and infinite
memory.
Solution is Memory Hierarchy.
In order of fastest to slowest, memory should be
assigned, considering cost as follows:
Registers
Internal CPU memory
Cache
Main memory
Memory on board external devices
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Cache
Cache memories rely on the
locality of reference principle.
Locality of reference

Refers to the address distance between

CPU
memory between consecutive code and
data access.
If the code or data fetched tends to reside
close in memory, then the locality of
referenceis
is low.
A cache
a relatively small storage of

Cache
Controller

L2 Cache

L1
Cache

fast memory where

frequently used instructions and data are kept.
Basic operations of Cache

Request for main memory access (read or write)

First, check cache for copy
cache hit: copy is in cache, quick access
cache miss: copy not in cache, read address and possibly its neighbors
into cache

Cache Hierarchy
L1 Cache: Nearest cache to CPU
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L2 Cache: Next level cache between L1 cache and Main
Memory
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Cache Access Time

tmain access time for main memory
tL1 access time for primary cache
h1 hit ratio of primary cache
tL2 access time for secondary cache
h2 hit ratio of secondary cache but not primary
If system has only L1 cache
Average access time, tav = h1tL1 + (1-h1)tmain
If system has L1 and L2 cache
Average access time, tav = h1tL1 + h2tL2 + (1-h1
-h2)tmain

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Cache Access Time Example

Problem:
Assume that the system has a two-level cache. The level-1 cache has
a hit rate of 90% and the level-2 cache has a hit rate of 97%. The level
1 cache access time is 4 ns, the level 2 cache access time is 15 ns and
access time of main memory is 80 ns. What is the average memory
access time?
Solution:
h1 = 0.9,
h2 = (1-0.9) X 0.97 = 0.1 X 0.97 = 0.097,
tL1 = 4 ns, tL2 = 15 ns, tmain = 80 ns.
tav = h1tL1 + h2tL2 + (1-h1-h2)tmain
= 0.9 X 4 ns + 0.097 X 15 ns + (1 0.9 0.097) X 80 ns
= 0.9 X 4 ns + 0.097 X 15 ns + 0.003 X 80 ns
= 3.6 ns + 1.455 ns + 0.24 ns
= 5.295 ns

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Watchdog Timer
Something goes unexpectedly wrong with your
program, and one piece of code (a subroutine)
keeps running, and running and running.
Watchdog Timer resets a stuck system.
Typically a timer that counts to zero
Reboots the system if counter reaches zero
For normal operation the software has to ensure
that the counter never reaches zero (kicking the
dog)

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