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Introduction
to
VERILOG HDL
What is HDL?
Hardware description language (HDL) is a
VHDL
1.
Based on C
2.
Case sensitive
Case insensitive
3.
4.
Predefined Datatypes
are available
Explicit Datatypes
Conversion is needed
HISTORY
1985: Verilog language and related simulator Verilog-XL were
Module Representation
Verilog provides the concept of module.
A module is a
Basic Building block in Verilog
It can be a single element or collection of lower design blocks
Syntax:
module <module-name>(inputs, outputs);
//Define inputs and outputs
endmodule
output [3:0] C;
Levels of Abstraction
There are Three different levels of abstraction in verilog:
Gate level
Data flow
Behavioral /Algorithmic
Design Block
GATE LEVEL
module practice (y, a, b); // module definition
input a, b;
// by default it takes 1 bit input
output y;
// one bit output
and gate_1(y, a, b) ;
endmodule
DATAFLOW LEVEL
// module definition
input a, b;
output y;
assign y = a & b;
endmodule
BEHAVIORAL LEVEL
FPGA SPARTAN 2 IC
RTL SCHEMATIC
OUTPUT WAVEFORM
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