GHANA TECHNOLOGY UNIVERSITY

COLLEGE- KUMASI CAMPUS

COMPUTER ARCHITECTURE
A PRESENTATION ON MEMORY HIERARCHY

(MAIN MEMORY)
GROUP 1

BIT LEVEL 200

FACULTY OF INFORMATICS

Sunday, November 20 , 2016

Group Members

Immanuel Owusu Boafo

040116425

Ishmael Haywoode
040116403

David Ayeliba
040116409

Ismael Ali Abdoulaye

040116276

INTRODUCTION
The Memory Hierarchy is a concept used to discuss
performance issues in computer architectural design,
algorithm predictions, and lower level programming
constructs involving locality of reference. The memory
hierarchy in computer storage separates each of its
levels based on response time. Since response time,
complexity, and capacity are related, the levels may also
be distinguished by their performance and controlling
technologies.
Multimedia I

 Each of the various components can be viewed as part of a

hierarchy of memories (m1,m2,...,mn) in which each member
mi is typically smaller and faster than the next highest
member mi+1 of the hierarchy. To limit waiting by higher
levels, a lower level will respond by filling a buffer and then
signaling to activate the transfer.
We are therefore forced to recognize the possibility of
constructing a hierarchy of memories, each of which has
greater capacity than the preceding but which is less quickly
accessible.
Multimedia I

THE FOUR MAJOR STORAGE LEVELS

INTERNAL Processor, Registers and Cache.
MAIN The System RAM and Controller Cards.
ON-LINE MASS STORAGE Secondary Storage.
OFF-LINE BULK STORAGE Tertiary and Off-line
Storage.
Multimedia I

An Example Memory
Hierarchy

Smaller,
faster,
and
costlier
(per byte)
storage
devices

Larger,
slower,
and
cheaper
(per byte)
storage
devices
L5:
Multimedia I

L0:
L1:
L2:

L3:

L4:

registers

on-chip L1
cache (SRAM)

CPU registers hold words retrieved

from L1 cache.

off-chip L2
cache (SRAM)

L1 cache holds cache lines retrieved

from the L2 cache memory.
L2 cache holds cache lines
retrieved from main memory.

main memory
(DRAM)

local secondary storage

(local disks)

Main memory holds disk

blocks retrieved from local
disks.

Local disks hold files

retrieved from disks on
remote network servers.

remote secondary storage

(tapes, distributed file systems, Web servers)
6

Random-Access Memory (RAM)

Key features
RAM is packaged as a chip
Basic storage unit is a cell (one bit per cell)
Multiple RAM chips form a memory

Static RAM (SRAM)

Each cell stores bit with a six-transistor circuit

Retains value indefinitely, as long as it is kept powered
Relatively insensitive to disturbances such as electrical noise
Faster and more expensive than DRAM

Dynamic RAM (DRAM)

Each cell stores bit with a capacitor and transistor

Value must be refreshed every 10-100 ms
Sensitive to disturbances
Slower and cheaper than SRAM
Multimedia I

Basic Types of RAM

RAM Random Access Memory
memory that can be both read and written during normal operation.

Contents are non-volatile, will be lost on power off.

Static RAM
Fast access time (used for off-processor cache)
Does not have to be refreshed
Dynamic RAM
Slower access time
Must be refreshed
much more dense
Multimedia I

Static RAM

Fastest access time of memory types. Typically the type of

RAM used primarily in Level -2 cache.
Read, Write operations take equal amounts of time.
Access to any random location takes same amount of time.
Basic memory cell is a latch, takes 6 transistors per memory
bit.
SRAM static - High Speed Memory that does not
require a refresh operation. Much faster than dynamic
RAM, with speeds between 8-12 nsec.
PBSRAM Pipeline Burst - Static RAM that has been
enhanced by the use of burst technology. Multiple
requests can be collected together and sent as a single
pipelined request. Bus speeds of 75MHz or higher.

Multimedia I

Static RAM Cell

Multimedia I

10

Dynamic RAM

Must be refreshed within less than a millisecond

Most main memory is dynamic RAM (least
expensive)
FPO Fast Page Mode Can only match speed of 30MHz
data bus
EDO Extended Data Out 66MHz motherboards or less
BEDO burst enhanced data-out
SDRAM Synchronous dynamic operates
synchronously with system clock and data bus. Can
handle 100MHz or more
DDR Double Data Rate can transmit data on both
edges of the clock
Multimedia I
11

Conventional DRAM Organization

d x w DRAM:

dw total bits organized as d supercells of

size w bits
0

addr

(to CPU)

2 bits
/

rows

memory
controller

1
supercell
(2,1)

2
8 bits
/

data
internal row buffer
Multimedia I

12

Reading DRAM
Supercell
(2,1)
Step 1(a): Row address
strobe (RAS) selects row 2
Step 1(b): Row 2 copied from DRAM array to row buffer
16 x 8 DRAM chip
0

RAS = 2
2
/

addr
rows

memory
controller

cols

1
2

8
/

data

internal row buffer

Reading DRAM Supercell (2,1)

Step 2(a): Column access strobe (CAS) selects column 1

Step 2(b): Supercell (2,1) copied from buffer to data lines,

and eventually back to CPU
16 x 8 DRAM chip
0

CAS = 1
2
/

rows

memory
controller
supercell
(2,1)

addr

To CPU

cols

1
2

8
/

data

Multimedia I

supercell
(2,1)

internal row buffer

14

SIMMS and DIMMS

Mount Memory Device Packages on Circuit Boards to

Conserve Space

30-Pin SIMM First Single Byte Access

Used in Pairs Since in x86 1 Word=16 bits

72-Pin SIMM Four Byte (32 bit) Access

Need Pairs for Pentium+ Since 64 bit Data Bus

168-pin DIMM Eight Byte (64 bit) Access

SIMM Single In-Line Memory Module

DIMM Dual In-Line Memory Module
Multimedia I

15

8M x 32 (32MB) SIMM

Multimedia I

16

Levels of Performance
Recall:
Dynamic Random Access Memory (DRAM)
Capacitors to store state (0 or 1)
Periodically refreshed
Relatively cheap

Static Random Access Memory (SRAM)

Transistors to store state
Doesnt need to be refreshed, faster, and uses less
power than DRAM
More expensive than DRAM
Multimedia I

17

BALANCING PERFORMANCE
WITH COST
Small memories
are fast but
expensive
Large memories are slow but
Persistence
cheap
Storing
data for lengthy periods of time
DRAM/SRAM is volatile: contents lost if power
lost
Disks are non-volatile: contents survive power
outages
To be useful, it must also be possible to find it
again later
Multimedia I
18
this brings in many interesting data organization,

Main Memory Technologies

Mask
Programmabl
e ROM

OTP
RO
M

UVEPR
OM

EEPRO
M

FLASH
MEMOR
Y

CACH
E
SRAM

SSRA
M

Volatile

DRA
M

SDRA
MM

Capacitor Storage Cell

x

Fastest Access Times

x
x

Core Memory SIMMS and DIMMS

Quartz-glass window

Support burst transfers using a clock

Requires periodic refreshing

Multimedia I

Highest Density
Fusible Links

Multiple programs and erases

without be removed

Nonvolatile and byte erasable

Cannot be programmed by user

x
x

x
X

19

THANK YOU
t

GHANA TECHNOLOGY UNIVERSITY

COLLEGE, KUMASI CAMPUS -