Computer Architecture 3rd Edition by Moris Mano CH 08

Central Processing Unit
CENTRAL PROCESSING UNIT

Introduction
General Register Organization
Stack Organization
Instruction Formats
Addressing Modes
Data Transfer and Manipulation
Program Control
Reduced Instruction Set Computer
Computer Organization
Computer Architectures Lab
Introduction
MAJOR COMPONENTS OF CPU

Storage Components
Registers
Flags
Execution(Processing) Components
Arithmetic Logic Unit(ALU)
Arithmetic calculations, Logical computations, Shifts/Rotates
Transfer Components
Bus
Control Components
Control Unit
Register
File
ALU
Control Unit
General Register Organization
GENERAL REGISTER ORGANIZATION
Input
Clock
R1
R2
R3
R4
R5
R6
R7
Load
(7 lines)
SELA
3x8
decoder
MUX
MUX
A bus
SELD
OPR
} SELB
B bus
ALU
Output
Control
OPERATION OF CONTROL UNIT

The control unit
Directs the information flow through ALU by
- Selecting various Components in the system
- Selecting the Function of ALU
Example: R1 <- R2 + R3
[1] MUX A selector (SELA): BUS A R2
[2] MUX B selector (SELB): BUS B R3
[3] ALU operation selector (OPR): ALU to ADD
[4] Decoder destination selector (SELD): R1 Out Bus
Control Word
3
SELA
3
SELB
3
SELD
5
OPR
Encoding of register selection fields

Binary
Code
000
001
010
011
100
101
110
111
SELA
Input
R1
R2
R3
R4
R5
R6
R7
SELB
Input
R1
R2
R3
R4
R5
R6
R7
SELD
None
R1
R2
R3
R4
R5
R6
R7
Control
ALU CONTROL
Encoding of ALU operations
OPR
Select
00000
00001
00010
00101
00110
01000
01010
01100
01110
10000
11000
Operation
Transfer A
Increment A
ADD A + B
Subtract A - B
Decrement A
AND A and B
OR A and B
XOR A and B
Complement A
Shift right A
Shift left A
Symbol
TSFA
INCA
ADD
SUB
DECA
AND
OR
XOR
COMA
SHRA
SHLA
Examples of ALU Microoperations

Symbolic Designation
Microoperation
SELA SELB
SELD
OPR
R1 R2 - R3
R4 R4 R5
R6 R6 + 1
R7 R1
Output R2
Output Input
R4 shl R4
R5 0
R2
R4
R6
R1
R2
Input
R4
R5
R1
R4
R6
R7
None
None
R4
R5
SUB
OR
INCA
TSFA
TSFA
TSFA
SHLA
XOR
R3
R5
R5
Control Word
010 011
100 101
110 000
001 000
010 000
000 000
100 000
101 101
001 00101
100 01010
110 00001
111 00000
000 00000
000 00000
100 11000
101 01100
Stack Organization
REGISTER STACK ORGANIZATION

Stack
- Very useful feature for nested subroutines, nested loops control
- Also efficient for arithmetic expression evaluation
- Storage which can be accessed in LIFO
- Pointer: SP
- Only PUSH and POP operations are applicable
stack
Register Stack
63
Flags
FULL
Address
EMPTY
Stack pointer
SP
Push, Pop operations
C
B
A
4
3
2
1
0
DR
/* Initially, SP = 0, EMPTY = 1, FULL = 0 */
PUSH
SP SP + 1
M[SP] DR
If (SP = 0) then (FULL 1)
EMPTY 0
POP
DR M[SP]
SP SP - 1
If (SP = 0) then (EMPTY 1)
FULL 0
Stack Organization
MEMORY STACK ORGANIZATION

1000
Memory with Program, Data,

and Stack Segments
PC
Program
(instructions)
AR
Data
(operands)
SP
- A portion of memory is used as a stack with a

processor register as a stack pointer
3000
stack
3997
3998
3999
4000
4001
DR
- PUSH: SP SP - 1
M[SP] DR
- POP:
DR M[SP]
SP SP + 1
- Most computers do not provide hardware to check
stack overflow (full stack) or underflow(empty stack)
Stack Organization
REVERSE POLISH NOTATION

Arithmetic Expressions: A + B
A + B Infix notation
+ A B Prefix or Polish notation
A B + Postfix or reverse Polish notation
- The reverse Polish notation is very suitable for stack
manipulation
Evaluation of Arithmetic Expressions
Any arithmetic expression can be expressed in parenthesis-free
Polish notation, including reverse Polish notation
(3 * 4) + (5 * 6)
4
3
12
5
12
34*56*+
6
5
12
30
12
42
Instruction Format
INSTRUCTION FORMAT
Instruction Fields
OP-code field - specifies the operation to be performed
Address field - designates memory address(es) or a processor register(s)
Mode field
- specifies the way the operand or the
effective address is determined
The number of address fields in the instruction format
depends on the internal organization of CPU
- The three most common CPU organizations:
Single accumulator organization:
ADD
X
/* AC AC + M[X] */
General register organization:
ADD
R1, R2, R3
/* R1 R2 + R3 */
ADD R1, R2
/* R1 R1 + R2 */
MOV R1, R2
/* R1 R2 */
ADD R1, X
/* R1 R1 + M[X] */
Stack organization:
PUSH X
/* TOS M[X] */
ADD
10
Instruction Format
THREE, AND TWO-ADDRESS INSTRUCTIONS

Three-Address Instructions
Program to evaluate X = (A + B) * (C + D) :
ADD R1, A, B
/* R1 M[A] + M[B]
ADD R2, C, D
/* R2 M[C] + M[D]
MUL X, R1, R2
/* M[X] R1 * R2
*/
*/
*/
- Results in short programs

- Instruction becomes long (many bits)
Two-Address Instructions
Program to evaluate X = (A + B) * (C + D) :
MOV
ADD
MOV
ADD
MUL
MOV
R1, A
R1, B
R2, C
R2, D
R1, R2
X, R1
/* R1 M[A]
/* R1 R1 + M[A]
/* R2 M[C]
/* R2 R2 + M[D]
/* R1 R1 * R2
/* M[X] R1
*/
*/
*/
*/
*/
*/
11
Instruction Format
ONE, AND ZERO-ADDRESS INSTRUCTIONS

One-Address Instructions
- Use an implied AC register for all data manipulation
- Program to evaluate X = (A + B) * (C + D) :
LOAD
A
/* AC M[A]
*/
ADD
B
/* AC AC + M[B] */
STORE
T
/* M[T] AC
*/
LOAD
C
/* AC M[C]
*/
ADD
D
/* AC AC + M[D] */
MUL
T
/* AC AC * M[T] */
STORE
X
/* M[X] AC
*/
Zero-Address Instructions
- Can be found in a stack-organized computer
- Program to evaluate X = (A + B) * (C + D) :
PUSH
PUSH
ADD
PUSH
PUSH
ADD
MUL
POP
A
B
C
D
X
/*
/*
/*
/*
/*
/*
/*
/*
TOS A
*/
TOS B
*/
TOS (A + B)
*/
TOS C
*/
TOS D
*/
TOS (C + D)
*/
TOS (C + D) * (A + B) */
M[X] TOS
*/
12
Addressing Modes
ADDRESSING MODES
Addressing Modes
* Specifies a rule for interpreting or modifying the
address field of the instruction (before the operand
is actually referenced)
* Variety of addressing modes
- to give programming flexibility to the user
- to use the bits in the address field of the
instruction efficiently
13
Addressing Modes
TYPES OF ADDRESSING MODES

Implied Mode
Address of the operands are specified implicitly
in the definition of the instruction
- No need to specify address in the instruction
- EA = AC, or EA = Stack[SP]
Immediate Mode
Instead of specifying the address of the operand,
operand itself is specified
- No need to specify address in the instruction
- However, operand itself needs to be specified
- Sometimes, require more bits than the address
- Fast to acquire an operand
Register Mode
Address specified in the instruction is the register address
- Designated operand need to be in a register
- Shorter address than the memory address
- Saving address field in the instruction
- Faster to acquire an operand than the memory addressing
- EA = IR(R) (IR(R): Register field of IR)
14
Addressing Modes

Register Indirect Mode
Instruction specifies a register which contains
the memory address of the operand
- Saving instruction bits since register address
is shorter than the memory address
- Slower to acquire an operand than both the
register addressing or memory addressing
- EA = [IR(R)] ([x]: Content of x)
Register used in Register Indirect Mode may have
Autoincrement or Autodecrement features
- When the address in the register is used to access memory, the
value in the register is incremented or decremented by 1
automatically
Direct Address Mode
Instruction specifies the memory address which
can be used directly to the physical memory
- Faster than the other memory addressing modes
- Too many bits are needed to specify the address
for a large physical memory space
- EA = IR(addr) (IR(addr): address field of IR)
15
Addressing Modes

Indirect Addressing Mode
The address field of an instruction specifies the address of a memory
location that contains the address of the operand
- When the abbreviated address is used large physical memory can be
addressed with a relatively small number of bits
- Slow to acquire an operand because of an additional memory access
- EA = M[IR(address)]
Relative Addressing Modes
The Address fields of an instruction specifies the part of the address
(abbreviated address) which can be used along with a designated
register to calculate the address of the operand
- Address field of the instruction is short
- Large physical memory can be accessed with a small number of
address bits
- EA = f(IR(address), R), R is sometimes implied
3 different Relative Addressing Modes depending on R;
* PC Relative Addressing Mode(R = PC)
- EA = PC + IR(address)
* Indexed Addressing Mode(R = IX, where IX: Index Register)
- EA = IX + IR(address)
* Base Register Addressing Mode(R = BAR, where BAR: Base Address Register)
- EA = BAR + IR(address)
16
Addressing Modes
ADDRESSING MODES
- EXAMPLES Address
PC = 200
200
201
202
Memory
Load to AC Mode
Address = 500
Next instruction
R1 = 400
XR = 100
399
400
450
700
500
800
600
900
702
325
800
300
AC
Addressing
Effective
Mode
Address
Direct address
500
Immediate operand Indirect address
800
Relative address
702
Indexed address
600
Register
Register indirect
400
Autoincrement
400
Autodecrement
399
/* AC (500)
/* AC 500
/* AC ((500))
/* AC (PC+500)
/* AC (RX+500)
/* AC R1
/* AC (R1)
/* AC (R1)+
/* AC -(R)
*/
*/
*/
*/
*/
*/
*/
*/
*/
Content
of AC
800
500
300
325
900
400
700
700
450
17
DATA TRANSFER INSTRUCTIONS

Typical Data Transfer Instructions
Name
Load
Store
Move
Exchange
Input
Output
Push
Pop
Mnemonic
LD
ST
MOV
XCH
IN
OUT
PUSH
POP
Data Transfer Instructions with Different Addressing Modes

Assembly
Mode
Convention
Direct address
LD ADR
Indirect address
LD @ADR
Relative address
LD $ADR
Immediate operand
LD #NBR
Index addressing
LD ADR(X)
Register
LD R1
Register indirect
LD (R1)
Autoincrement
LD (R1)+
Autodecrement
LD -(R1)
Register Transfer
AC M[ADR]
AC M[M[ADR]]
AC M[PC + ADR]
AC NBR
AC M[ADR + XR]
AC R1
AC M[R1]
AC M[R1], R1 R1 + 1
R1 R1 - 1, AC M[R1]
18
DATA MANIPULATION INSTRUCTIONS

Three Basic Types: Arithmetic instructions
Logical and bit manipulation instructions
Shift instructions
Arithmetic Instructions
Name
Increment
Decrement
Add
Subtract
Multiply
Divide
Add with Carry
Subtract with Borrow
Negate(2s Complement)
Mnemonic
INC
DEC
ADD
SUB
MUL
DIV
ADDC
SUBB
NEG
Logical and Bit Manipulation Instructions

Name
Mnemonic
Clear
CLR
Complement
COM
AND
AND
OR
OR
Exclusive-OR
XOR
Clear carry
CLRC
Set carry
SETC
Complement carry COMC
Enable interrupt EI
Disable interrupt DI
Shift Instructions
Name
Logical shift right
Logical shift left
Arithmetic shift right
Arithmetic shift left
Rotate right
Rotate left
Rotate right thru carry
Rotate left thru carry
Mnemonic
SHR
SHL
SHRA
SHLA
ROR
ROL
RORC
ROLC
19
Program Control
PROGRAM CONTROL INSTRUCTIONS

+1
In-Line Sequencing
(Next instruction is fetched from the
next adjacent location in the memory)
PC
Address from other source; Current Instruction, Stack, etc

Branch, Conditional Branch, Subroutine, etc
Program Control Instructions

Name
Branch
Jump
Skip
Call
Return
Compare(by - )
Test(by AND)
Status Flag Circuit
Mnemonic
BR
JMP
SKP
CALL
RTN
CMP
TST
B
* CMP and TST instructions do not retain their

results of operations(- and AND, respectively).
They only set or clear certain Flags.
c7
c8
V Z S C
8-bit ALU
F7 - F0
F7
8
Check for
zero output
F
20
Program Control
CONDITIONAL BRANCH INSTRUCTIONS

Mnemonic Branch condition
BZ
BNZ
BC
BNC
BP
BM
BV
BNV
Branch if zero
Branch if not zero
Branch if carry
Branch if no carry
Branch if plus
Branch if minus
Branch if overflow
Branch if no overflow
Tested condition
Z=1
Z=0
C=1
C=0
S=0
S=1
V=1
V=0
Unsigned compare conditions (A - B)

BHI
Branch if higher
A>B
BHE
Branch if higher or equal
A B
BLO
Branch if lower
A<B
BLOE Branch if lower or equal
A B
BE
Branch if equal
A=B
BNE
Branch if not equal
A B
Signed compare conditions (A - B)
BGT
Branch if greater than
A>B
BGE
Branch if greater or equal
A B
BLT
Branch if less than
A<B
BLE
Branch if less or equal
A B
BE
Branch if equal
A=B
BNE
Branch if not equal
A B
21
Program Control
SUBROUTINE CALL AND RETURN

SUBROUTINE CALL
Call subroutine
Jump to subroutine
Branch to subroutine
Branch and save return address
Two Most Important Operations are Implied;

* Branch to the beginning of the Subroutine
- Same as the Branch or Conditional Branch
* Save the Return Address to get the address
of the location in the Calling Program upon
exit from the Subroutine
- Locations for storing Return Address
Fixed Location in the subroutine(Memory)
Fixed Location in memory
In a processor Register
In a memory stack
- most efficient way
CALL
SP SP - 1
M[SP] PC
PC EA
RTN
PC M[SP]
SP SP + 1
22
Program Control
PROGRAM INTERRUPT
Types of Interrupts
External interrupts
External Interrupts initiated from the outside of CPU and Memory
- I/O Device -> Data transfer request or Data transfer complete
- Timing Device -> Timeout
- Power Failure
- Operator
Internal interrupts (traps)
Internal Interrupts are caused by the currently running program
- Register, Stack Overflow
- Divide by zero
- OP-code Violation
- Protection Violation
Software Interrupts
Both External and Internal Interrupts are initiated by the computer HW.
Software Interrupts are initiated by the executing an instruction.
- Supervisor Call -> Switching from a user mode to the supervisor mode
-> Allows to execute a certain class of operations
which are not allowed in the user mode
23
Program Control
INTERRUPT PROCEDURE
Interrupt Procedure and Subroutine Call
- The interrupt is usually initiated by an internal or
an external signal rather than from the execution of
an instruction (except for the software interrupt)
- The address of the interrupt service program is
determined by the hardware rather than from the
address field of an instruction
- An interrupt procedure usually stores all the
information necessary to define the state of CPU
rather than storing only the PC.
The state of the CPU is determined from;
Content of the PC
Content of all processor registers
Content of status bits
Many ways of saving the CPU state
depending on the CPU architectures
24
RISC: REDUCED INSTRUCTION SET COMPUTERS
RIS
C
Historical Background
IBM System/360, 1964
- The real beginning of modern computer architecture
- Distinction between Architecture and Implementation
- Architecture: The abstract structure of a computer
seen by an assembly-language programmer
High-Level
Language
Compiler
Instruction
Set
Architecture
-program
Hardware
Implementation
Continuing growth in semiconductor memory and microprogramming

-> A much richer and complicated instruction sets
=> CISC(Complex Instruction Set Computer)
- Arguments advanced at that time
Richer instruction sets would simplify compilers
Richer instruction sets would alleviate the software crisis
- move as much functions to the hardware as possible
- close Semantic Gap between machine language
and the high-level language
Richer instruction sets would improve architecture quality
25
ARCHITECTURE DESIGN PRINCIPLES
RISC
- IN 70s -
* Large microprograms would add little or nothing

to the cost of the machine
<- Rapid growth of memory technology
-> Large General Purpose Instruction Set
* Microprogram is much faster than the machine instructions
<- Microprogram memory is much faster than main memory
-> Moving the software functions into
Microprogram for the high performance machines
* Execution speed is proportional to the program size
-> Architectural techniques that led to small program
-> High performance instruction set
* Number of registers in CPU has limitations
-> Very costly
-> Difficult to utilize them efficiently
26
RISC
COMPARISONS OF EXECUTION MODELS

A B + C
Data: 32-bit
Register-to-register
8
Load
Load
Add
Store
16
rB
rC
rA
rA
B
C
rC
A
rB
I = 104b; D = 96b; M = 200b

Memory-to-register
8
Load
Add
Store
16
B
C
A
I = 72b; D = 96b; M = 168b

Memory-to-memory
8
16
16
16
Add
I = 56b; D = 96b; M = 152b

27
RISC
FOUR MODERN ARCHITECTURES IN 70s

IBM 370/168
DEC
VAX-11/780
Intel
Xerox
Dorado
iAPX-432
Year
1973
1978
1978
1982
# of instrs.
208
303
270
222
Control mem. size
420 Kb
480 Kb
136 Kb
420 Kb
Instr. size (bits)
16-48
16-456
8-24
6-321
Technology
ECL MSI
TTL MSI
ECL MSI
NMOS VLSI
Execution model
reg-mem
mem-mem
reg-reg
reg-mem
mem-mem
reg-reg
stack
stack
mem-mem
Cache size
64 Kb
64 Kb
64 Kb
64 Kb
Changes in the Implementation World in 70s

* Main Memory is no longer 10 times slower than
Microprogram memory
-> microprogram rather slows down the speed
* Caches had been invented
-> Further improvement on the Main Memory speed
* Compilers were subsetting architectures
28
RISC
CRITICISM ON COMPLEX INSTRUCTION SET COMPUTERS

Complex Instruction Set Computers - CISC
High Performance General Purpose Instructions
- Complex Instruction
-> Format, Length, Addressing Modes
-> Complicated instruction cycle control due to the complex
decoding HW and decoding process
- Multiple memory cycle instructions
-> Operations on memory data
-> Multiple memory accesses/instruction
- Microprogrammed control is necessity
-> Microprogram control storage takes
substantial portion of CPU chip area
-> Semantic Gap is large between machine
instruction and microinstruction
- General purpose instruction set includes all the features required
by individually different applications
-> When any one application is running, all the features
required by the other applications are extra burden to
the application
29
RISC
PHYLOSOPHY OF RISC
Reduce the semantic gap between
machine instruction and microinstruction
1-Cycle instruction
Most of the instructions complete their execution
in 1 CPU clock cycle - like a microoperation
* Functions of the instruction (contrast to CISC)
- Very simple functions
- Very simple instruction format
- Similar to microinstructions
=> No need for microprogrammed control
* Register-Register Instructions
- Avoid memory reference instructions except
Load and Store instructions
- Most of the operands can be found in the
registers instead of main memory
=> Shorter instructions
=> Uniform instruction cycle
=> Requirement of large number of registers
* Employ instruction pipeline
30
RISC
ARCHITECTURAL METRIC
A B + C
B A + C
D D - B
Register-to-register (Reuse of Operands)
8
Load
Load
Add
Store
Add
Store
Load
Sub
Store
16
rB
B
C
rC
rA rB rC
rA
A
rB rA rC
rB
B
rD
D
rD rD rB
rD
D
I = 228b
D = 192b
M = 420b
Register-to-register (Compiler allocates Operands in registers)

8
Add
Add
Sub
Memory-to-memory
rA
rB
rD
rB
rA
rD
rC
rC
rB
I = 60b
D = 0b
M = 60b
16
16
16
Add
Add
Sub
B
A
B
C
C
D
A
B
D
I = 168b
D = 288b
M = 456b
31
RISC
CHARACTERISTICS OF RISC
Common RISC Characteristics
- Operations are register-to-register, with only LOAD and
STORE accessing memory
- The operations and addressing modes are reduced
Instruction formats are simple and do not cross
word boundaries
- RISC branches avoid pipeline penalties - delayed branch.
Characteristics of Initial RISC Machines
Year
Number of
instructions
Control memory
size
Instruction
size (bits)
Technology
Execution model
IBM 801
1980
RISC I
1982
MIPS
1983
120
39
55
32
NMOS VLSI
reg-reg
32
NMOS VLSI
reg-reg
32
ECL MSI
reg-reg
32
RISC
COMPARISON OF INSTRUCTION SEQUENCE

32b memory port
A B+C
A A+ 1
DD-B
OP
RISC 1
VAX
DEST
rA
rB
register
operand
rC
ADD
rA
rA
immediate
operand
SUB
rD
rD
register
operand
rB
ADD
(3 operands)
register
operand
INC
(1 operands)
register
operand
SUB
(2 operands)
register
operand
register
operand
C ...
... C
1 operand
in memory
2 operands
in memory
... D
register
operand
3 operands
in memory
A
D
D
I
N
C
SOUR2
ADD
register
operand
432
SOUR1
A
D
D
I
N
C
D ...
SUB
33
RISC
TWO INITIAL APPROACHES TO RISC

Two Approaches to utilizing RISC registers
The Register Window Approach
- A large number of registers to store variables
- Berkeley RISC I, RISC II
The Optimizing Compiler Approach
- A smart compiler to allocate variables most efficiently to registers
- IBM 801, Stanford MIPS
<Weighted Relative Dynamic Frequency of HLL Operations>
Dynamic
Occurrence
ASSIGN
LOOP
CALL
IF
GOTO
Other
Pascal
45
5
15
29
6
C
38
3
12
43
3
1
MachineInstruction
Weighted
Pascal
C
13
13
42
32
31
33
11
21
3
Memory
Reference
Weighted
Pascal
C
14
15
33
26
44
45
7
13
2
=> The procedure call/return is the most time-consuming operations

in typical HLL programs
34
RISC
REGISTER WINDOW APPROACH

Observations
- Weighted Dynamic Frequency of HLL Operations
=> Procedure call/return is the most time consuming operations
- Locality of Procedure Nesting
=> The depth of procedure activation fluctuates
within a relatively narrow range
- A typical procedure employs only a few passed
parameters and local variables
Solution
- Use multiple small sets of registers (windows),
each assigned to a different procedure
- A procedure call automatically switches the CPU to use a different
window of registers, rather than saving registers in memory
- Windows for adjacent procedures are overlapped
to allow parameter passing
35
RISC
CALL-RETURN BEHAVIOR
Call-return behavior as a function of nesting depth and time
36
RISC
CIRCULAR OVERLAPPED REGISTER WINDOWS
37
RISC
OVERLAPPED REGISTER WINDOWS

R73
R25
R64
R63
R16
R15
R31
R58
R57
R10
R26
Proc D
R25
Local to D
Common to C and D
Local to C
R48
R47
R16
R15
R31
R42
R41
R10
R26
Proc C
R25
Common to B and C
Local to B
R32
R16
R31
R15
R31
R26
R10
R26
R25
Proc B
R25
Local to A
R16
R15
R10
R9
R16
R31
R15
Common
R26 to D and A
R10
R9
Common to all
procedures
R0
Common to A and B
Common to A and D
Proc A
R0
Global
registers
38
RISC
BERKELEY RISC I
- 32-bit integrated circuit CPU
- 32-bit address, 8-, 16-, 32-bit data
- 32-bit instruction format
- total 31 instructions
- three addressing modes:
register; immediate; PC relative addressing
- 138 registers
10 global registers
8 windows of 32 registers each
Berkeley RISC I Instruction Formats
Regsiter mode: (S2 specifies a register)
31
24 23
19 18
14 13 12
Opcode
Rd
Rs
5 4
Not used
8
Rd
PC relative mode
31
24 23
Opcode
COND
Rs
S2
13
19 18
5
S2
5
Register-immediate mode (S2 specifies an operand)

31
24 23
19 18
14 13 12
Opcode
Y
19
39
RISC
INSTRUCTION SET OF BERKELEY RISC I

Opcode
Operands
Register Transfer
Data manipulation instructions

ADD
Rs,S2,Rd
Rd
ADDC
Rs,S2,Rd
Rd
SUB
Rs,S2,Rd
Rd
SUBC
Rs,S2,Rd
Rd
SUBR
Rs,S2,Rd
Rd
SUBCR
Rs,S2,Rd
Rd
AND
Rs,S2,Rd
Rd
OR
Rs,S2,Rd
Rd
XOR
Rs,S2,Rd
Rd
SLL
Rs,S2,Rd
Rd
SRL
Rs,S2,Rd
Rd
SRA
Rs,S2,Rd
Rd
Data transfer instructions
LDL
(Rs)S2,Rd
LDSU
(Rs)S2,Rd
LDSS
(Rs)S2,Rd
LDBU
(Rs)S2,Rd
LDBS
(Rs)S2,Rd
LDHI
Rd,Y
STL
Rd,(Rs)S2
STS
Rd,(Rs)S2
STB
Rd,(Rs)S2
GETPSW Rd
PUTPSW Rd
Rs + S2
Rs + S2 + carry
Rs - S2
Rs - S2 - carry
S2 - Rs
S2 - Rs - carry
Rs S2
Rs S2
Rs S2
Rs shifted by S2
Rs shifted by S2
Rs shifted by S2
Rd M[Rs + S2]
Rd M[Rs + S2]
Rd M[Rs + S2]
Rd M[Rs + S2]
Rd M[Rs + S2]
Rd Y
M[Rs + S2] Rd
M[Rs + S2] Rd
M[Rs + S2] Rd
Rd PSW
PSW Rd
Description
Integer add
Add with carry
Integer subtract
Subtract with carry
Subtract reverse
Subtract with carry
AND
OR
Exclusive-OR
Shift-left
Shift-right logical
Shift-right arithmetic
Load long
Load short unsigned
Load short signed
Load byte unsigned
Load byte signed
Load immediate high
Store long
Store short
Store byte
Load status word
Set status word
Opcode
Operands
40
Register Transfer
Description
Program control instructions

JMP
COND,S2(Rs) PC Rs + S2
Conditional jump
JMPR
COND,Y
PC PC + Y
Jump relative
CALL
Rd,S2(Rs)
Rd PC, PC Rs + S2 Call subroutine and
CWP CWP - 1
change window
CALLR
Rd,Y
Rd PC, PC PC + Y Call relative and
CWP CWP - 1
change window
RET
Rd,S2
PC Rd + S2
Return and
CWP CWP + 1
change window
CALLINT Rd
Rd PC,CWP CWP - 1 Call an interrupt pr.
RETINT
Rd,S2
PC Rd + S2
Return from
CWP CWP + 1
interrupt pr.
GTLPC
Rd
Rd PC
Get last PC
41
RISC
CHARACTERISTICS OF RISC
RISC Characteristics
- Relatively few instructions
- Relatively few addressing modes
- Memory access limited to load and store instructions
- All operations done within the registers of the CPU
- Fixed-length, easily decoded instruction format
- Single-cycle instruction format
- Hardwired rather than microprogrammed control
Advantages of RISC
- VLSI Realization
- Computing Speed
- Design Costs and Reliability
- High Level Language Support
42
RISC
ADVANTAGES OF RISC
VLSI Realization
Control area is considerably reduced
Example:
RISC I: 6%
RISC II: 10%
MC68020: 68%
general CISCs: ~50%
--> RISC chips allow a large number of registers on the chip

- Enhancement of performance and HLL support
- Higher regularization factor and lower VLSI design cost
The GaAs VLSI chip realization is possible
Computing Speed
- Simpler, smaller control unit --> faster
- Simpler instruction set; addressing modes;instruction format
--> faster decoding
- Register operation --> faster than memory operation
- Register window --> enhances the overall speed of execution
- Identical instruction length, One cycle instruction execution
--> suitable for pipelining --> faster
43
RISC
ADVANTAGES OF RISC
Design Costs and Reliability
- Shorter time to design
--> reduction in the overall design cost and
reduces the problem that the end product will
be obsolete by the time the design is completed
- Simpler, smaller control unit
--> higher reliability
- Simple instruction format (of fixed length)
--> ease of virtual memory management
High Level Language Support
- A single choice of instruction
--> shorter, simpler compiler
- A large number of CPU registers
--> more efficient code
- Register window
--> Direct support of HLL
- Reduced burden on compiler writer

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CENTRAL PROCESSING UNIT

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MAJOR COMPONENTS OF CPU

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General Register Organization

GENERAL REGISTER ORGANIZATION

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OPERATION OF CONTROL UNIT

Encoding of register selection fields

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Examples of ALU Microoperations

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REGISTER STACK ORGANIZATION

Push, Pop operations

/* Initially, SP = 0, EMPTY = 1, FULL = 0 */

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Memory with Program, Data,

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ONE, AND ZERO-ADDRESS INSTRUCTIONS

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TYPES OF ADDRESSING MODES

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TYPES OF ADDRESSING MODES

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Data Transfer and Manipulation

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Data Transfer Instructions with Different Addressing Modes

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Logical and Bit Manipulation Instructions

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Address from other source; Current Instruction, Stack, etc

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