Computer Arithmetic

COMPUTER ARITHMETIC

Arithmetic with Signed-2's Complement Numbers

Multiplication and Division
Floating-Point Arithmetic Operations
Decimal Arithmetic Unit
Decimal Arithmetic Operations

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Computer Arithmetic

Addition and Subtraction

SIGNED MAGNITUDEADDITION AND SUBTRACTION

Addition:
A + B ; A: Augend; B: Addend
Subtraction: A - B: A: Minuend; B: Subtrahend
Operation
(+A) + (+B)
(+A) + (- B)
(- A) + (+B)
(- A) + (- B)
(+A) - (+B)
(+A) - (- B)
(- A) - (+B)
(- A) - (- B)

Add
Magnitude
+(A + B)
- (A + B)
+(A + B)
- (A + B)

Subtract Magnitude
When A>B When A<B When A=B
+(A - B)
- (A - B)

- (B - A)
+(B - A)

+(A - B)
+(A - B)

+(A - B)

- (B - A)

+(A - B)

- (A - B)

+(B - A)

+(A - B)

Hardware Implementation

Bs

AVF
E

B Register

Complementer

Output
Carry

Parallel Adder

M(Mode Control)
Input
Carry

S
As
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A Register

Load Sum
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Computer Arithmetic

Addition and Subtraction

SIGNED 2S COMPLEMENT ADDITION AND SUBTRACTION

Hardware
B Register

Complementer and
Parallel Adder

V
Overflow

AC

Algorithm
Subtract

Minuend in AC
Subtrahend in B

Augend in AC
Addend in B

AC AC + B+ 1
V overflow

AC AC + B
V overflow

END
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Add

END
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Computer Arithmetic

Multiplication

MULTIPLICATION
Multiplication: B * A; B: Multiplicand; A: Multiplier; P: Partial Product
Multiplication of Unsigned Positive Numbers
A = An-1An-2 ... A0
B = Bn-1Bn-2 ... B0
P = B * An-1
= B * ( 2i * Ai )
i=0

= An-1 * (B2n-1) + An-2 * (B2n-2) + ... + A0 * (B20)

B shifted left
n-1 bits

B shifted left
n-2 bits

B shifted left
0 bits = A

Or
B shifted (n-1) bits to the left

P = An-1*(B2n-1 * 20) + An-2*(B2n-1 * 2-1) + ... + A0*(B2n-1 * 2-(n-1))

B2n-1

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B2n-1 shifted right

1 bit

B2n-1 shifted right

(n-1) bits
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Computer Arithmetic

Multiplication

EXAMPLE

Multiplicand B=10111

Multiplier in Q
Q0 = 1; add B
First partial product
Shift right EAQ
Q0 = 1; add B
Second Partial Product
Shift right EAQ
Q0 = 0; shift right EAQ
Q0 = 0; shift right EAQ
Q0 = 1; add B
Fifth partial product
Shift right EAQ
Final Product in AQ = 0110110101

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0
0
1
0
0
0
0
0

00000
10111
10111
01011
10111
00010
10001
01000
00100
10111
11011
01101

SC

10011

101

11001

100

01100
10110
01011

011
010
001

10101

000

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Computer Arithmetic

Multiplication

SIGNED MAGNITUDE MULTIPLICATION

Bs

Hardware

B Register

Sequence Counter

Complementer and
Parallel Adder
As
0

Qn

Qs

AC

Q Register

EAQ
B <- Multiplicand B
Q <- MultiplierA

Algorithm
As,Qs <- Qs Bs
A <- 0, E <- 0
SC <- n-1
= 0 Q =1
0
EA <- A + B

END
Product
in AQ

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=0

=0

shr EAQ
SC <- SC+1

SC

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Computer Arithmetic

Multiplication

BOOTH MULTIPLICATION ALGORITHM FOR SIGNED 2S

COMPLEMENT
Multiplier
Strings of 0s: No addition; Simply shifts
Strings of 1s: String of 1s from mp to mq:

2p+1 - 2q

Example
001110 (14) -> p = 3, q = 1
001110 = 23+1 - 21
M * 14 = M24 - M21
Algorithm
[1] Subtract multiplicand for the first least significant 1
in a string of 1s in the multiplier
[2] Add multiplicand for the first 0 after the string
of 1s in the multiplier
[3] Partial Product does not change when the
multiplier bit is identical to the previous bit
110010 = -24 + 22 - 21 = -16 + 4 - 2 = -14
subtract
24

Add
22

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subtract
21
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Computer Arithmetic

Multiplication

BOOTH ALGORITHM FOR SIGNED 2S COMPLEMENT

B <- Multiplicand B
Q <- Multiplier A
AC <- 0
Q-1 <- 0
SC <- n
Q0Q-1
?

10

01

Q-1 : shifted out bit

on shr of Q

11
00
AC<-AC+B+1

AC <- AC + B

ashr(AC&Q)
SC <- SC + 1
0

SC
?
=0
END

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Computer Arithmetic

Multiplication

EXAMPLE OF BOOTH MULTIPLIER

Q0Q-1
10

B = 10111
B+1=01001
Initial
Subtract B

11
01

ashr
ashr
Add B

00
10

ashr
ashr
Subtract B
ashr

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AC
00000
01001
01001
00100
00010
10111
11001
11100
11110
01001
00111
00011

Q
10011

Q -1
0

SC
101

11001
01100

1
1

100
011

10110
01011

0
0

010
001

10101

000

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Computer Arithmetic

Multiplication

ARRAY MULTIPLIER
A = a1a0: Multiplier
B = b1b0: Multiplicand
C = B * A = c3c2c1c0
c3

a1b1
c2

b1
b0
a1
a0
a0b1 a0b0
a 1b0
c1
c0
b1

b0

a0

a1

b1

b0

HA
C S
c3
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c2

HA
C
S
c 1 c0
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Computer Arithmetic

Multiplication

ARRAY MULTIPLIER 4-BIT X 3-BIT

a0

b3

a1

b3

b2

b1

b2

b1

b0

b0
0

Addend

Augend

4-bit Adder
Sum and Carry Outputs

a2
b3

b2

b1

b0

Addend

Augend

4-bit Adder
Sum and Carry Outputs

c6
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c5

c4

c3

c2

c1

c0
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Computer Arithmetic

Division

DIVISION
A/ B = Q + R

A: Dividend; B: Divisor; Q: Quotient; R: Remainder

Divisor B = 10001, B+ 1 = 01111

E
A
01110
Dividend:
0
11100
shl EAQ
01111
add B+1
1
01011
E=1
1
01011
Set Q0=1
0
10110
shl EAQ
01111
Add B+1
1
00101
E=1
1
00101
Set Q0=1
0
01010
shl EAQ
01111
add B+1
0
11001
E=0; Q0=0
10001
add B
1
01010
restore remainder
0
10100
shl EAQ
01111
add B+1
1
00011
E=1
1
00011
Set Q0=1
0
00110
shl EAQ
01111
add B+1
0
10101
E=0; Q0=0
10001
add B
1
00110
restore remainder
neglect E
00110
remainder in A
quotient in Q
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Q
00000
00000

SC
5

00001
00010

00011
00110

00110
01100
01101
11010

11010
11010

11010
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Computer Arithmetic

Division

FLOWCHART OF DIVIDE OPERATION

Dividend in AQ
Divisor in B

Qs As Bs
SC<- n - 1

shl EAQ
E

EA A + B+1
1

A B

EA A+B+1

0
A<B

A A+B+1

0(A<B)
EA A+B
DVF 1

EA A+B
DVF 0

A B
Q0 1

EA A+B

SC SC-1

END
(Divide overflow)

SC

END
(Quotient in Q
Remainder in R)
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Computer Arithmetic

Floating Point Arithmetic

FLOATING POINT ARITHMETIC OPERATIONS

F = m x re
where m: Mantissa
r: Radix
e: Exponent
Registers for Floating Point Arithmetic

Bs

Parallel Adder

As A1
Qs

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BR

Parallel Adder
and Comparator

AC

QR

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Computer Arithmetic

Floating Point Arithmetic

FLOATING POINT ADD AND AUBTRACT

C
H
E
C
K
F
O
R

=0 BR 0

AC

=0

a<b

AC<-BR
add

a>b

a:b

shr A
a <- a+1

op
sub
As<-As

shr B
b <- b+1

sub

As Bs
0

EA<-A+B+1
A<-A+1
As<-As

add

op

As Bs

Align
Mantissa

0
0

E
A

A1

EA<-A+B

=0
AC<-0

shl A
a<-a+1

+ or - of
mantissa

Normalization

shr A
A1<-E
a<-a+1
END

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Computer Arithmetic

Floating Point Arithmetic

FLOATING POINT MULTIPLICATION

BR <- Multiplicand
QR <- Multiplier
=0

BR
0

=0

QR
0

AC <- 0

a <- q
a <- a+b
a <- a-bias
Multiply mantissa
(finxed point
multiplication)
shl AQ
a <- a-1

A1
1

END
(Product is in AC)

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Computer Arithmetic

Floating Point Arithmetic

FLOATING POINT DIVISION

BR<-Divisor
AC<-Dividend
=0
=0
QR <- 0

BR
0
AC
0

Qs <- As + Bs
Q<-0
SC<-n-1

divide
by 0

EA <- A+B+1
1

0
A<B

A>=B
A <- A+B
shr A
a <- a+1

A <- A+B

a <- a+b+1
a <- a+bias
q <- a
Divide Magnitude of mantissa
as in fixed point numbers
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Computer Arithmetic

BCD Arithmetic

BCD ADD
BCD digit < 10
BCD digit + BCD digit + carry =< 19
K
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1

Binary Sum
Z8 Z4 Z2 Z1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1

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C
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1

BCD Sum
S8 S4 S2 S1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1

Decimal
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
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Computer Arithmetic

BCD Arithmetic

BCD ADDER
If we can convert Binary Sums to BCD Sum ,
we can use a binary adder to add two BCD numbers
SUM =< 9
BCD Sum = Binary Sum
BCD Carry = Binary Carry

19 >= SUM > 9

BCD Sum = Binary Sum + 0110
BCD Carry = Carry(Binary Sum + 0110)

4-bit Binary Add

1

Take next
higher digit
Z8

1
1

Z4

done
?

0
1
BCD Sum<-Sum + 0110
BCD C<-Carry(BCD Sum)

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Z2

END

0
BCD Sum = Sum
BCD C<-Carry(Sum)

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Computer Arithmetic

BCD Arithmetic

BCD ADDER HARDWARE

Addend

Carry Out

Augend

4-bit Binary Addr

Z8

Z4

Z2

Carry In

Z1

BCD Carry

0
0110
4-bit Binary Adder

S 8 S 4 S 2 S1
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Computer Arithmetic

Decimal Arithmetic

DECIMAL ARITHMETIC OPERATIONS

Addition
- Identical to the BCD addition
- 9s complement and 10s complement are
identical to 1s complement and 10s
complement, respectively

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