Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
Power Dissipation
and
Additional Design Constraints
(Lecture #14)
The slides included herein were taken from the materials accompanying
Fundamentals of Logic Design, 6th Edition, by Roth and Kinney,
and were used with permission from Cengage Learning.
Material to be covered
Supplemental
Chapter 8: Sections 1 5
Fall 2010
Power Dissipation
Fall 2010
Power Dissipation
PT = PS + PD
Fall 2010
PS = VCC * ICC
Fall 2010
74LS00 Datasheet
Fall 2010
Supply voltage
Fall 2010
Supply current
High output:
ICCmax = 1.6 mA
Low output:
ICCmax = 4.4 mA
High output:
Low output:
PS = 8.4 mW
PS = 23.1 mW
Duty Cycle
Fall 2010
PS_high = 8.4 mW
PS_low = 23.1 mW
Assume PS = 0
PD >> PS
Fall 2010
CT = CPD + CL
Fall 2010
10
Low High
High Low
Fall 2010
11
74HC00 Datasheet
Fall 2010
12
VDD = 5V
CPD = 20 pF, CL = 50 pF
PD
1K
1.8 W
1M
100M
Fall 2010
1.8 mW
180 mW
ECE 331 - Digital System Design
13
74HC00 Datasheet
Fall 2010
14
VCC = 5V
ICC = 20 A
Fall 2010
PT = PS + PD
where PD is a function of fT
ECE 331 - Digital System Design
15
PT = PS + PD
1 MHz
100 MHz
TTL
15.8 mW
15.8 mW
15.8 mW
CMOS
100 W
1.805 mW
180 mW
Fall 2010
TTL
CMOS
PS
VCC * ICC
VDD * IDD
PD
~0W
16
Hazards
Fall 2010
17
Hazards
When the input to a combinational logic circuit changes,
unwanted switching transients may appear on the output.
These transients occur when different paths from input to
output have different propagation delays.
Fall 2010
18
Hazards
Fall 2010
19
Hazards
Fall 2010
20
Hazards
Fall 2010
21
Fall 2010
22
Fall 2010
23
Fall 2010
24
Fall 2010
25
Fall 2010
26
27
Hazards
Exercise:
Design a hazard-free combinational logic circuit
to implement the following logic function
F(A,B,C) = A'.C' + A.D + B.C.D'
Fall 2010
28
Hazards
Exercise:
Design a hazard-free combinational logic circuit
to implement the following logic function
F(A,B,C) = (A'+C').(A+D).(B+C+D')
Fall 2010
29
Hazards
Why?
Fall 2010
Why?
30
Questions?
Fall 2010
31