3D Transistors

By

Karanvir
Singh
10105EN065

CONTENTS

Introduction to 3D transistors
Need for 3D transistors
Operation
Comparison with 2D transistors
Advantages
Applications
Conclusion
References

Introduction
3D transistors employ a single gate stacked on top
of two vertical gates allowing for essentially three
times the surface area for electrons to travel,
without increasing the size of the gate.
The Gate is the terminal that drives the transistor
on and off, and acts like a capacitance where
charge is stored making the channel conductive.
When the gate is charged, it creates an inversion
layer between the Source and the Drain,
where electrons can flow.

Moores Law

The number of transistors on an integrated circuit

doubles approximately every two years which is
achieved by scaling down the transistor size.

Need for 3D transistors

Silicon-only planar transistors are fast approaching their

scaling limit.
Short channel effects limiting scaling into sub nanometer
regime.
Oxide thickness cannot be scaled down further, problems
of tunneling.
Need to keep Silicon technology as the base technology
while innovating future devices; cost is an important
factor.
Performance and power dissipation need to be improved.
Smaller is faster !!

Planar MOSFET Scaling (Short-Channel Effect)

Lg = 0.35 m, Tox = 8 nm

Lg = 0.18 m, Tox = 4.5 nm

Short-Channel Effect

Short-Channel Effect

Lg = 0.10 m, Tox = 2.5 nm

Lg = 0.07 m, Tox = 1.9 nm

a. DIBL (Drain Induced Barrier Lowering) effect

shifts the characteristics to the left when VD is
increased.
b. S increases when the channel length is
decreased.

Operation
3D or Tri-Gate transistors form conducting channels
on three sides of a vertical fin structure, providing
fully depleted operation and tighter control on
the channel.

Tri-gate transistor

The additional control enables as much transistor

current flowing as possible when the transistor is in
the 'on' state (for performance), and as close to
zero as possible when it is in the 'off' state (to
minimize power), and enables the transistor to
switch very quickly between the two states (again,
for performance) due to improved sub-threshold
slope and increased inversion layer area provides
higher drive currents.

2 D Planar transistor

Transistor
characteristics

Planar MOSFET

3D Transistor

Steeper subthreshold slope

that reduces
leakage current.
Better switching
operation.

The steeper sub-threshold slope can also be used to target a

lower threshold voltage, allowing transistors to operate at
lower voltage to reduce power and/or improve switching
speed.

Transistor Gate Delays

2D vs. 3D transistor

22 nm 3D Tri-Gate
transistors can
operate at lower
voltage with good
performance,
reducing active
power by >50%

Advantages

Dramatic performance gain at low operating

voltage, better than Bulk Planar transistor
37% performance increase at low voltage
>50% power reduction at constant performance
Improved switching characteristics (On current
vs. Off current)
Higher drive current for a given transistor
footprint implies better performance
More compact hence enabling higher transistor
density which translates to smaller overall
microelectronics.

Integration challenges

The primary challenges to integrating non planar

tri-gate devices into conventional semiconductor
manufacturing processes include:
Fabrication of a thin silicon "fin" tens of
nanometers wide
Fabrication of matched gates on multiple sides of
the fin

Conclusion
The new chip technology, called tri-gate
transistors, replaces flat, two-dimensional streams
of transistors with a 3D structure.
The technology will allow manufacturers to create
transistors that are faster, smaller and more powerefficient which will be used in the next generation
of desktops, laptops and mobile chips.
Tri-Gate transistors are an important innovation
needed to continue Moores Law.

References

[1] Isabelle Ferain, Cynthia A. Colinge & Jean-Pierre Colinge,

Multigate transistors as the future of classical metal-oxide
semiconductor field effects transistors.
[2] Aniket A. Breed/ Dr. Marc Cahay, Design and Evolution of
modern SOI fully-depleted MOSFETs.
[3] Jack Kavalieros, Brian Doyle, Tri-Gate Transistor
Architecture with High-k Gate Dielectrics, Metal Gates.
[4] Viranjay M. Srivastava, Setu P. Singh, Analysis and
Design of Tri-Gate MOSFET with High Dielectrics Gate.
[5] http://en.wikipedia.org/wiki/Multigate_device
[6] http
://www.intel.com/content/www/us/en/energy/intel-22nm-3-d-tri
-gate-transistor-technology.html

Thank you