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SDH Basics

System Engineering
Introduction of SDH

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Synchronous Digital Hirarcy

System Engineering
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Table of Contens

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What?....For Whom?....What For?

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Chapter 1 : Principles of PDH Multiplexing

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1. Principles of PDH Multiplexing

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1. Principles of PDH Multiplexing

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1.1 Objectives

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1.2 ANSI/CEPT Bit Rates

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1.2 ANSI/CEPT Bit Rates

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1.2 ANSI/CEPT Bit Rates

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1.3 Frame Structures of a PDH SIgnal

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1.4 Multiplexing/Demultiplexing of PDH Signals

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1.4 Multiplexing/Demultiplexing of PDH Signals

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1.4 Multiplexing/Demultiplexing of PDH Signals

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1.4 Multiplexing/Demultiplexing of PDH Signals

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1.4 Multiplexing/Demultiplexing of PDH Signals

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1.4 Multiplexing/Demultiplexing of PDH Signals

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1.5 Summary

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1.6 Test

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1.6 Test

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Chapter 2 : Characteristics of SDH

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Principles and Characteristics of SDH

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2.1 Objectives

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2.2 Definition Synchronous Network

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2.2 Definition Syncrhonous Network

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2.2 Definition Synchronous Network

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2.3 ITU-T Bit Rates in SDH

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2.4 Structure of an STM-1 frame

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2.4 Structure of an STM-1 frame

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2.4 Structure of an STM-1 frame

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2.4 Structure of an STM-1 frame

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2.5 Byte by Byte Multiplexing of SDH Signals

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2.5 Byte by Byte Multiplexing of SDH Signals

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2.5 Byte by Byte Multiplexing of SDH Signals

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2.5 Byte by Byte Multiplexing of SDH Signals

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2.6 Synchronization of STM-1 Frame

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2.7 Optical Line Code in the SDH

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2.8 Summary

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2.9 Test

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2.9 Test

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Chapter 3 : Mapping

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3. Mapping

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3.1 Objectives

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3.2 140 Mbit/s STM-1

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3.2.1 Mapping of a 140 Mbit/s Signal to the Container C-4

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3.2.1 Mapping of a 140 Mbit/s Signal to the Container C-4

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3.2.1 Mapping of a 140 Mbit/s Signal to the Container C-4

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3.2.2 Interleaving of the C-4 into the STM-1

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3.2.2 Interleaving of the C-4 into the STM-1

VC-4

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3.2.2 Interleaving of the C-4 into the STM-1

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3.2.2 Interleaving of the C-4 into the STM-1

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3.2.2 Interleaving of the C-4 into the STM-1

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3.2.2 Interleaving of the C-4 into the STM-1

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3.2.2 Interleaving of the C-4 into the STM-1

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3.2.2 Interleaving of the C-4 into the STM-1

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3.3 3x34 Mbit/s STM-1

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3.3.1 Mapping of a 34 Mbit/s Signal to the Container C-3

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3.3.1 Mapping of a 34 Mbit/s Signal to the Container C-3

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3.3.1 Mapping of a 34 Mbit/s Signal to the Container C-3

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3.3.1 Mapping of a 34 Mbit/s Signal to the Container C-3

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3.3.2 Interleaving of three C-3 into the VC-4

VC-3

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3.3.2 Interleaving of three C-3 into the VC-4

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3.3.2 Interleaving of three C-3 into the VC-4

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3.3.2 Interleaving of three C-3 into the VC-4

TUG-3

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3.3.2 Interleaving of three C-3 into the VC-4

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3.3.2 Interleaving of three C-3 into the VC-4

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3.3.2 Interleaving of three C-3 into the VC-4

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3.3.2 Interleaving of three C-3 into the VC-4

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3.3.2 Interleaving of three C-3 into the VC-4

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3.4 63x2 Mbit/s STM1

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3.4.1 Mapping of a 2Mbit/s Signal to the Container C-12

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3.4.1 Mapping of a 2Mbit/s Signal to the Container C-12

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3.4.1 Mapping of a 2Mbit/s Signal to the Container C-12

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3.4.2 Creating a VC-12 Multiframe

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3.4.2 Creating a VC-12 Multiframe

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3.4.3 Creating Tributary Units

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3.4.3 Creating Tributary Units

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3.4.3 Creating Tributary Units

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3.4.3 Creating Tributary Units

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3.4.3 Creating Tributary Units

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3.4.3 Creating Tributary Units

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3.4.3 Creating Tributary Units

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3.4.4 Interleaving of the VC-4 into STM-1

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3.4.4 Interleaving of the VC-4 into STM-1

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3.4.4 Interleaving of the VC-4 into STM-1

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3.5 ATM Cells STM-1

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3.5.1 Basic Structure and Contents of ATM an Cell

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3.5.1 Basic Structure and Contents of ATM an Cell

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3.5.2 Mapping of ATM Cells to the Container C-4

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3.5.2 Mapping of ATM Cells to the Container C-4

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3.5.3 Interleaving of the VC-4 into STM-1

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3.5.3 Interleaving of the VC-4 into STM-1

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3.5.3 Interleaving of the VC-4 into STM-1

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3.5.3 Interleaving of the VC-4 into STM-1

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3.6 Summary

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3.6 Summary

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3.6 Summary

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3.6 Summary

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3.6 Summary

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3.6 Summary

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3.7 Test

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3.7 Test

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Chapter 4 : Pointer

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4. Pointer

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4.1 Objectives

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4.2 AU-4 Pointer

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4.2.1 Addressing the VC-4

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4.2.1 Addressing the VC-4

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4.2.2 Negative Justification

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4.2.2 Negative Justification

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4.2.2 Negative Justification

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4.2.2 Negative Justification

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4.2.3 Positive Justification

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4.2.3 Positive Justification

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4.2.3 Positive Justification

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4.2.4 AU-4 Pointer Structure

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4.2.4 AU-4 Pointer Structure

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4.2.4 AU-4 Pointer Structure

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4.2.4 AU-4 Pointer Structure

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4.2.4 AU-4 Pointer Structure

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4.2.4 AU-4 Pointer Structure

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4.3 TU-3 Pointer

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4.3.1 Addressing the VC-3

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4.3.1 Addressing the VC-3

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4.3.1 Addressing the VC-3

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4.3.1 Addressing the VC-3

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4.3.2 TU-3 Pointer Structure

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4.3.2 TU-3 Pointer Structure

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4.3.2 TU-3 Pointer Structure

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4.3.2 TU-3 Pointer Structure

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4.4 TU-12 Pointer

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4.4.1 Addressing the Multiframe VC-12

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4.4.1 Addressing the Multiframe VC-12

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4.4.1 Addressing the Multiframe VC-12

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4.4.1 Addressing the Multiframe VC-12

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4.4.2 TU-12 Pointer Structure

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4.4.2 TU-12 Pointer Structure

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4.4.2 TU-12 Pointer Structure

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4.4.2 TU-12 Pointer Structure

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4.4.2 TU-12 Pointer Structure

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4.5 Summary

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4.5 Summary

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4.5 Summary

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4.6 Test

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4.6 Test

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Chapter 5 : Overhead

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5. Overhead

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5.1 Objectives

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5.2 Overhead Function

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5.3 Description and Charateristics of Section Overhead (SOH)

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5.3 Description and Charateristics of Section Overhead (SOH)

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5.3 Description and Charateristics of Section Overhead (SOH)

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5.3 Description and Charateristics of Section Overhead (SOH)

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5.3 Description and Charateristics of Section Overhead (SOH)

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5.3 Description and Charateristics of Section Overhead (SOH)

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5.3 Description and Charateristics of Section Overhead (SOH)

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5.3 Description and Charateristics of Section Overhead (SOH)

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5.3 Description and Charateristics of Section Overhead (SOH)

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5.3 Description and Charateristics of Section Overhead (SOH)

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5.3 Description and Charateristics of Section Overhead (SOH)

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5.3 Description and Charateristics of Section Overhead (SOH)

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5.3 Description and Charateristics of Section Overhead (SOH)

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5.3 Description and Charateristics of Section Overhead (SOH)

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5.3 Description and Charateristics of Section Overhead (SOH)

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5.3 Description and Charateristics of Section Overhead (SOH)

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5.3 Description and Charateristics of Section Overhead (SOH)

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5.3 Description and Charateristics of Section Overhead (SOH)


The data communication channel D1-D12 are
transmiited
in the STM-1#1 of the multiplex signal
(STM-4) only
The S1 Byte (timing marker) is only transmiited in the
STM-1#1 of the multiplex signal (STM-4)
The Z1 and Z2 bytes of every single STM-1 frame are
transmitted in the multiplex signal (STM-4).
Execption : S1 and M1 bytes
The M1 byte (Multiplex Section FEBE) is transmitted at
the position of the THIRD Z2 byte in the multiplex signal
(STM-4)

The STM-1 identification C1 of every single STM-1 frame is transmitted in


the multiplex signal (STM-4)
The B2 Bytes of every single STM-1 frame are transmitted in the multiplex
signal
The Bytes K1 and K2 (automatic protection swithing signaling) are
transmitted in the STM1#1 of the multiplex signal (STM-4) only
The B1 Bytes is transmitted in the STM1#1 of the multiplex signal only
The Order Wire Channel E1 and E2 are transmitted in STM-1#1 of the
multiplex signal (STM-4) only
The user channel F1 is transmiited in STM-1#1 of the multiplex signal (STM-4)
only

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5.4 Path Overhead

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5.4.1 Description and Characteristics of the VC-4 POH

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5.4.1 Description and Characteristics of the VC-4 POH

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5.4.1 Description and Characteristics of the VC-4 POH

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5.4.1 Description and Characteristics of the VC-4 POH

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5.4.1 Description and Characteristics of the VC-4 POH

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5.4.1 Description and Characteristics of the VC-4 POH

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5.4.1 Description and Characteristics of the VC-4 POH

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5.4.1 Description and Characteristics of the VC-4 POH

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5.4.2 Description and Characteristics of the VC-3 POH

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5.4.2 Description and Characteristics of the VC-3 POH

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5.4.2 Description and Characteristics of the VC-3 POH

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5.4.2 Description and Characteristics of the VC-3 POH

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5.4.2 Description and Characteristics of the VC-3 POH

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5.4.2 Description and Characteristics of the VC-3 POH

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5.4.2 Description and Characteristics of the VC-3 POH

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5.4.3 Description and Characteristics of the VC-12 POH

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5.4.3 Description and Characteristics of the VC-12 POH

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5.4.3 Description and Characteristics of the VC-12 POH

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5.4.3 Description and Characteristics of the VC-12 POH

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5.5 Affected Area of Overhead

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5.6 Summary

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5.6 Summary

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5.7 Test

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5.7 Test

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5.7 Test

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Chapter 6 : Monitoring

System Engineering
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6. Monitoring, Maintenance and Control

System Engineering
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6.1 Objectives

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6.2 SDH Bit Error Monitoring

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6.2.1 Bit Interleave Parity (BIP)

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6.2.1 Bit Interleave Parity (BIP)

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6.2.1 Bit Interleave Parity (BIP)

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6.2.1 Bit Interleave Parity (BIP)

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6.2.1 Bit Interleave Parity (BIP)

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6.2.2 Bytes for Bit Error Monitoring

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6.2.2 Bytes for Bit Error Monitoring

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6.2.2 Bytes for Bit Error Monitoring

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6.2.2 Bytes for Bit Error Monitoring

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6.2.3 Bite Error Monitoring Concept (Examples)

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6.2.3 Bite Error Monitoring Concept (Examples)

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6.2.3 Bite Error Monitoring Concept (Examples)

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6.2.3 Bite Error Monitoring Concept (Examples)

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6.2.3 Bite Error Monitoring Concept (Examples)

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6.2.3 Bite Error Monitoring Concept (Examples)

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6.2.3 Bite Error Monitoring Concept (Examples)

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6.3 Error and Failure Report

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6.3 Error and Failure Report

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6.3 Error and Failure Report

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6.3 Error and Failure Report

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6.3 Error and Failure Report

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6.3 Error and Failure Report

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6.3 Error and Failure Report

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6.4 Alarm Indication Signal (AIS)

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6.4 Alarm Indication Signal (AIS)

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6.4 Alarm Indication Signal (AIS)

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6.4 Alarm Indication Signal (AIS)

A cable Break is indicated in the Regenerator


by the alarm Loss Of Signal (LOS)
The regenerator can not re-generate the STM-4
signal and sends Section AIS
The Mux-2 transmit all-one-signals on channels
1, 2 and 3. The PDH devices interpret these
signals as AIS

The Mux-2 send Path AIS (Pointer+VC-4 =1)


in channel#4. The las SDH Mux (MUX 3) also
send AIS to thePDH device.

Error report are issued in the backward


direction, too. MUX 2 send Section FERF and
Path FERF for paths #1, #2 and #3 to MUX 1 .

System Engineering
Introduction of SDH

MUX 3 sends Path FERF for channel#4, which is


swithed trough until the end of the path (MUX 1)

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6.5 Summary

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6.5 Summary

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6.5 Summary

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6.5 Summary

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6.6 Test

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6.6 Test

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